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Remove predicated pseudo-instructions.
These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
098c6a547f
commit
f632d80e0c
@ -4016,48 +4016,6 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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// Conditional instructions
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multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
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Instruction irsr,
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InstrItinClass iii, InstrItinClass iir,
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InstrItinClass iis> {
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def ri : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rfalse, GPR:$Rn, so_imm:$imm,
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pred:$p, cc_out:$s),
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4, iii, [],
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(iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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def rr : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rfalse, GPR:$Rn, GPR:$Rm,
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pred:$p, cc_out:$s),
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4, iir, [],
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(irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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def rsi : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rfalse, GPR:$Rn, so_reg_imm:$shift,
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pred:$p, cc_out:$s),
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4, iis, [],
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(irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rfalse, GPRnopc:$Rn, so_reg_reg:$shift,
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pred:$p, cc_out:$s),
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4, iis, [],
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(irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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}
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defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm ADDCC : AsI1_bincc_irs<ADDri, ADDrr, ADDrsi, ADDrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm SUBCC : AsI1_bincc_irs<SUBri, SUBrr, SUBrsi, SUBrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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} // neverHasSideEffects
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@ -774,33 +774,6 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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let Inst{24} = 1;
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let Inst{23-21} = op23_21;
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}
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// Predicated versions.
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def CCri : t2PseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_imm:$imm,
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pred:$p, cc_out:$s), 4, IIC_iALUi, [],
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(!cast<Instruction>(NAME#ri) GPRnopc:$Rd,
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GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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def CCri12 : t2PseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rfalse, GPR:$Rn, imm0_4095:$imm,
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pred:$p),
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4, IIC_iALUi, [],
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(!cast<Instruction>(NAME#ri12) GPRnopc:$Rd,
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GPR:$Rn, imm0_4095:$imm, pred:$p)>,
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RegConstraint<"$Rfalse = $Rd">;
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def CCrr : t2PseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rfalse, GPRnopc:$Rn, rGPR:$Rm,
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pred:$p, cc_out:$s), 4, IIC_iALUr, [],
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(!cast<Instruction>(NAME#rr) GPRnopc:$Rd,
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GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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def CCrs : t2PseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rfalse, GPRnopc:$Rn, t2_so_reg:$Rm,
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pred:$p, cc_out:$s), 4, IIC_iALUsi, [],
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(!cast<Instruction>(NAME#rs) GPRnopc:$Rd,
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GPRnopc:$Rn, t2_so_reg:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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}
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/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
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@ -3069,37 +3042,6 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
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RegConstraint<"$false = $Rd">;
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} // isCodeGenOnly = 1
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multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
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// shifted imm
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def ri : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rfalse, rGPR:$Rn, t2_so_imm:$imm,
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pred:$p, cc_out:$s),
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4, iii, [],
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(iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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// register
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def rr : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rfalse, rGPR:$Rn, rGPR:$Rm,
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pred:$p, cc_out:$s),
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4, iir, [],
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(irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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// shifted register
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def rs : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rfalse, rGPR:$Rn, t2_so_reg:$ShiftedRm,
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pred:$p, cc_out:$s),
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4, iis, [],
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(irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rfalse = $Rd">;
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} // T2I_bincc_irs
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defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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