mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-16 11:24:39 +00:00
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
@@ -104,234 +104,6 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
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}
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static void StoreRegToStackSlot(const TargetInstrInfo &TII,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) {
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if (RC == PPC::GPRCRegisterClass) {
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if (SrcReg != PPC::LR) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
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.addReg(PPC::R11, false, false, isKill), FrameIdx));
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (SrcReg != PPC::LR8) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
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.addReg(PPC::X11, false, false, isKill), FrameIdx));
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::F4RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
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.addReg(SrcReg, false, false, isKill), FrameIdx));
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} else if (RC == PPC::CRRCRegisterClass) {
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// FIXME: We use R0 here, because it isn't available for RA.
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// We need to store the CR in the low 4-bits of the saved value. First,
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// issue a MFCR to save all of the CRBits.
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NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
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// If the saved register wasn't CR0, shift the bits left so that they are in
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// CR0's slot.
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if (SrcReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
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// rlwinm r0, r0, ShiftBits, 0, 31.
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NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
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}
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
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.addReg(PPC::R0, false, false, isKill), FrameIdx));
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R0 = ADDI FI#
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// STVX VAL, 0, R0
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
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FrameIdx, 0, 0));
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NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
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.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void
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PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC) const {
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SmallVector<MachineInstr*, 4> NewMIs;
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StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs);
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for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
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MBB.insert(MI, NewMIs[i]);
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}
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void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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if (Addr[0].isFrameIndex()) {
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StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
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return;
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}
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unsigned Opc = 0;
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if (RC == PPC::GPRCRegisterClass) {
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Opc = PPC::STW;
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} else if (RC == PPC::G8RCRegisterClass) {
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Opc = PPC::STD;
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} else if (RC == PPC::F8RCRegisterClass) {
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Opc = PPC::STFD;
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} else if (RC == PPC::F4RCRegisterClass) {
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Opc = PPC::STFS;
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} else if (RC == PPC::VRRCRegisterClass) {
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Opc = PPC::STVX;
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) {
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if (RC == PPC::GPRCRegisterClass) {
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if (DestReg != PPC::LR) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
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FrameIdx));
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} else {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
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FrameIdx));
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NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (DestReg != PPC::LR8) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
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FrameIdx));
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} else {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
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FrameIdx));
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NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
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FrameIdx));
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} else if (RC == PPC::F4RCRegisterClass) {
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
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FrameIdx));
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} else if (RC == PPC::CRRCRegisterClass) {
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// FIXME: We use R0 here, because it isn't available for RA.
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
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FrameIdx));
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// If the reloaded register isn't CR0, shift the bits right so that they are
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// in the right CR's slot.
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if (DestReg != PPC::CR0) {
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unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
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// rlwinm r11, r11, 32-ShiftBits, 0, 31.
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NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
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}
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NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R0 = ADDI FI#
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// Dest = LVX 0, R0
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
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FrameIdx, 0, 0));
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NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
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.addReg(PPC::R0));
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void
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PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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SmallVector<MachineInstr*, 4> NewMIs;
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LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs);
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for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
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MBB.insert(MI, NewMIs[i]);
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}
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void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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if (Addr[0].isFrameIndex()) {
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LoadRegFromStackSlot(TII, DestReg, Addr[0].getIndex(), RC, NewMIs);
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return;
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}
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unsigned Opc = 0;
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if (RC == PPC::GPRCRegisterClass) {
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assert(DestReg != PPC::LR && "Can't handle this yet!");
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Opc = PPC::LWZ;
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} else if (RC == PPC::G8RCRegisterClass) {
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assert(DestReg != PPC::LR8 && "Can't handle this yet!");
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Opc = PPC::LD;
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} else if (RC == PPC::F8RCRegisterClass) {
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Opc = PPC::LFD;
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} else if (RC == PPC::F4RCRegisterClass) {
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Opc = PPC::LFS;
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} else if (RC == PPC::VRRCRegisterClass) {
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Opc = PPC::LVX;
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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