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R600: Replace big texture opcode switch in scheduler by usesTC/usesVC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-05-17 16:50:37 +00:00
parent 4ed9917147
commit f63f85affa
1 changed files with 3 additions and 23 deletions

26
lib/Target/R600/R600MachineScheduler.cpp

@ -243,6 +243,9 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
int R600SchedStrategy::getInstKind(SUnit* SU) {
int Opcode = SU->getInstr()->getOpcode();
if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
return IDFetch;
if (TII->isALUInstr(Opcode)) {
return IDAlu;
}
@ -255,30 +258,7 @@ int R600SchedStrategy::getInstKind(SUnit* SU) {
case AMDGPU::INTERP_VEC_LOAD:
case AMDGPU::DOT_4:
return IDAlu;
case AMDGPU::TEX_VTX_CONSTBUF:
case AMDGPU::TEX_VTX_TEXBUF:
case AMDGPU::TEX_LD:
case AMDGPU::TEX_GET_TEXTURE_RESINFO:
case AMDGPU::TEX_GET_GRADIENTS_H:
case AMDGPU::TEX_GET_GRADIENTS_V:
case AMDGPU::TEX_SET_GRADIENTS_H:
case AMDGPU::TEX_SET_GRADIENTS_V:
case AMDGPU::TEX_SAMPLE:
case AMDGPU::TEX_SAMPLE_C:
case AMDGPU::TEX_SAMPLE_L:
case AMDGPU::TEX_SAMPLE_C_L:
case AMDGPU::TEX_SAMPLE_LB:
case AMDGPU::TEX_SAMPLE_C_LB:
case AMDGPU::TEX_SAMPLE_G:
case AMDGPU::TEX_SAMPLE_C_G:
case AMDGPU::TXD:
case AMDGPU::TXD_SHADOW:
return IDFetch;
default:
DEBUG(
dbgs() << "other inst: ";
SU->dump(DAG);
);
return IDOther;
}
}