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Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses;
and fixed CustomInserter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122607 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1012,6 +1012,8 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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@ -1024,8 +1026,6 @@ SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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BB->addSuccessor(sinkMBB);
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BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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@ -233,7 +233,8 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence. This has to handle all
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// permutations of selection between i32/f32/f64 on ICC and FCC.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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let Uses = [ICC],
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usesCustomInserter = 1 in { // Expanded after instruction selection.
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def SELECT_CC_Int_ICC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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@ -244,6 +245,9 @@ let usesCustomInserter = 1 in { // Expanded after instruction selection.
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond))]>;
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}
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let usesCustomInserter = 1, Uses = [FCC] in {
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def SELECT_CC_FP_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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@ -440,24 +444,29 @@ defm ADDX : F3_12<"addx", 0b001000, adde>;
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// Section B.15 - Subtract Instructions, p. 110
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defm SUB : F3_12 <"sub" , 0b000100, sub>;
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defm SUBX : F3_12 <"subx" , 0b001100, sube>;
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let Uses = [ICC] in
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defm SUBX : F3_12 <"subx" , 0b001100, sube>;
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let Defs = [ICC] in {
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let Defs = [ICC] in
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defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
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let Uses = [ICC], Defs = [ICC] in
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def SUBXCCrr: F3_1<2, 0b011100,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst", []>;
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}
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// Section B.18 - Multiply Instructions, p. 113
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defm UMUL : F3_12np<"umul", 0b001010>;
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defm SMUL : F3_12 <"smul", 0b001011, mul>;
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let Defs = [Y] in {
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defm UMUL : F3_12np<"umul", 0b001010>;
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defm SMUL : F3_12 <"smul", 0b001011, mul>;
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}
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// Section B.19 - Divide Instructions, p. 115
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defm UDIV : F3_12np<"udiv", 0b001110>;
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defm SDIV : F3_12np<"sdiv", 0b001111>;
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let Defs = [Y] in {
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defm UDIV : F3_12np<"udiv", 0b001110>;
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defm SDIV : F3_12np<"sdiv", 0b001111>;
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}
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// Section B.20 - SAVE and RESTORE, p. 117
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defm SAVE : F3_12np<"save" , 0b111100>;
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@ -527,18 +536,20 @@ let Uses = [O0, O1, O2, O3, O4, O5],
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}
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// Section B.28 - Read State Register Instructions
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def RDY : F3_1<2, 0b101000,
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(outs IntRegs:$dst), (ins),
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"rd %y, $dst", []>;
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let Uses = [Y] in
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def RDY : F3_1<2, 0b101000,
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(outs IntRegs:$dst), (ins),
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"rd %y, $dst", []>;
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// Section B.29 - Write State Register Instructions
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def WRYrr : F3_1<2, 0b110000,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"wr $b, $c, %y", []>;
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def WRYri : F3_2<2, 0b110000,
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(outs), (ins IntRegs:$b, i32imm:$c),
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"wr $b, $c, %y", []>;
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let Defs = [Y] in {
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def WRYrr : F3_1<2, 0b110000,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"wr $b, $c, %y", []>;
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def WRYri : F3_2<2, 0b110000,
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(outs), (ins IntRegs:$b, i32imm:$c),
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"wr $b, $c, %y", []>;
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}
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3<2, 0b110100, 0b011000100,
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(outs FPRegs:$dst), (ins FPRegs:$src),
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@ -45,6 +45,9 @@ class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
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def ICC : SparcCtrlReg<"ICC">;
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def FCC : SparcCtrlReg<"FCC">;
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// Y register
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def Y : SparcCtrlReg<"Y">;
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// Integer registers
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def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
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def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
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