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Add a special handling case for untyped CopyFromReg node in GetCostForDef() of ScheduleDAGRRList

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Weiming Zhao 2013-01-29 21:18:43 +00:00
parent 02c953ea8b
commit f662a59b8b
1 changed files with 11 additions and 1 deletions
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12
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -21,6 +21,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/DataLayout.h"
@ -274,8 +275,17 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
// the expansion of custom DAG-to-DAG patterns.
if (VT == MVT::Untyped) {
const SDNode *Node = RegDefPos.GetNode();
unsigned Opcode = Node->getMachineOpcode();
// Special handling for CopyFromReg of untyped values.
if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
RegClass = RC->getID();
Cost = 1;
return;
}
unsigned Opcode = Node->getMachineOpcode();
if (Opcode == TargetOpcode::REG_SEQUENCE) {
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);