6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

ARM push of a single register encodes as pre-indexed STR.

Browse Source 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-08-11 18:07:11 +00:00
parent 5c1ff1f2f2
commit f6713916fb
4 changed files with 25 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@@ -2879,6 +2879,22 @@ processInstruction(MCInst &Inst,
Inst = TmpInst;
}
break;
case ARM::STMDB_UPD:
// If this is a store of a single register via a 'push', then we should use
// a pre-indexed STR instruction instead, per the ARM ARM.
if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
Inst.getNumOperands() == 5) {
MCInst TmpInst;
TmpInst.setOpcode(ARM::STR_PRE_IMM);
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
TmpInst.addOperand(MCOperand::CreateImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
}
break;
}
}