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Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-10-27 21:08:32 +00:00
parent 8d51a3286f
commit f686d9b71f
3 changed files with 25 additions and 6 deletions
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11
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2868,6 +2868,17 @@ bool X86::isSplatMask(SDNode *N) {
return ::isSplatMask(N);
}
/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a splat of zero element.
bool X86::isSplatLoMask(SDNode *N) {
assert(N->getOpcode() == ISD::BUILD_VECTOR);
for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
if (!isUndefOrEqual(N->getOperand(i), 0))
return false;
return true;
}
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
/// instructions.

4
lib/Target/X86/X86ISelLowering.h
View File

@ -225,6 +225,10 @@ namespace llvm {
/// specifies a splat of a single element.
bool isSplatMask(SDNode *N);
/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a splat of zero element.
bool isSplatLoMask(SDNode *N);
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
/// instructions.

16
lib/Target/X86/X86InstrSSE.td
View File

@ -104,8 +104,8 @@ def SSE_splat_mask : PatLeaf<(build_vector), [{
return X86::isSplatMask(N);
}], SHUFFLE_get_shuf_imm>;
def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
return X86::isSplatMask(N);
def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
return X86::isSplatLoMask(N);
}]>;
def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
@ -812,13 +812,13 @@ def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
"movddup {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v2f64 (vector_shuffle
VR128:$src, (undef),
SSE_splat_v2_mask)))]>;
SSE_splat_lo_mask)))]>;
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
"movddup {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v2f64 (vector_shuffle
(scalar_to_vector (loadf64 addr:$src)),
(undef),
SSE_splat_v2_mask)))]>;
SSE_splat_lo_mask)))]>;
// SSE2 instructions without OpSize prefix
def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@ -1908,10 +1908,14 @@ def : Pat<(v4f32 (vector_shuffle immAllZerosV,
// Splat v2f64 / v2i64
let AddedComplexity = 10 in {
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
(UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
(PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
}
// Splat v4f32