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Thumb parsing and encoding for SUB (SP minu immediate).

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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-24 21:42:27 +00:00
parent 12a1e3bbcb
commit f69c804036
3 changed files with 19 additions and 11 deletions
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10
lib/Target/ARM/ARMInstrThumb.td
View File

@ -335,10 +335,6 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
let DecoderMethod = "DecodeThumbAddSPImm"; let DecoderMethod = "DecodeThumbAddSPImm";
} }
// Can optionally specify SP as a three operand instruction.
def : tInstAlias<"add${p} sp, sp, $imm",
(tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
// SUB sp, sp, #<imm7> // SUB sp, sp, #<imm7>
// FIXME: The encoding and the ASM string don't match up. // FIXME: The encoding and the ASM string don't match up.
def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
@ -350,6 +346,12 @@ def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
let DecoderMethod = "DecodeThumbAddSPImm"; let DecoderMethod = "DecodeThumbAddSPImm";
} }
// Can optionally specify SP as a three operand instruction.
def : tInstAlias<"add${p} sp, sp, $imm",
(tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
def : tInstAlias<"sub${p} sp, sp, $imm",
(tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
// ADD <Rm>, sp // ADD <Rm>, sp
def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr, def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
"add", "\t$Rdn, $sp, $Rn", []>, "add", "\t$Rdn, $sp, $Rn", []>,

10
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -2923,9 +2923,13 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
static_cast<ARMOperand*>(Operands[1])->getReg() == 0) static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
return true; return true;
// Register-register 'add' for thumb does not have a cc_out operand // Register-register 'add/sub' for thumb does not have a cc_out operand
// when it's an ADD SP, #imm. // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
// right, this will result in better diagnostics (which operand is off)
// anyway.
if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
(Operands.size() == 5 || Operands.size() == 6) &&
static_cast<ARMOperand*>(Operands[3])->isReg() && static_cast<ARMOperand*>(Operands[3])->isReg() &&
static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
static_cast<ARMOperand*>(Operands[1])->getReg() == 0) static_cast<ARMOperand*>(Operands[1])->getReg() == 0)

10
test/MC/ARM/basic-thumb-instructions.s
View File

@ -538,11 +538,13 @@ _func:
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ FIXME: SUB (SP minus immediate) @ SUB (SP minus immediate)
@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
@ FIXME: SUB (SP minus register)
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
sub sp, #12
sub sp, sp, #508
@ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
@ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------