mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
Remove more special cases from LegalizeDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72456 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
47b41f7e20
commit
f6b23bfc79
@ -154,6 +154,12 @@ private:
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}
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SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
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SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
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RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
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RTLIB::Libcall Call_PPCF128);
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SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
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RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
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RTLIB::Libcall Call_I128);
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SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
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SDValue ExpandBUILD_VECTOR(SDNode *Node);
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@ -625,20 +631,6 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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return DAG.getMergeValues(Ops, 2, dl);
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}
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/// GetFPLibCall - Return the right libcall for the given floating point type.
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static RTLIB::Libcall GetFPLibCall(MVT VT,
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RTLIB::Libcall Call_F32,
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RTLIB::Libcall Call_F64,
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RTLIB::Libcall Call_F80,
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RTLIB::Libcall Call_PPCF128) {
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return
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VT == MVT::f32 ? Call_F32 :
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VT == MVT::f64 ? Call_F64 :
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VT == MVT::f80 ? Call_F80 :
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VT == MVT::ppcf128 ? Call_PPCF128 :
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RTLIB::UNKNOWN_LIBCALL;
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}
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/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
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/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
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/// is necessary to spill the vector being inserted into to memory, perform
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@ -772,8 +764,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::CALLSEQ_END:
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case ISD::SELECT_CC:
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case ISD::SETCC:
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case ISD::EXCEPTIONADDR:
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case ISD::EHSELECTION:
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// These instructions have properties that aren't modeled in the
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// generic codepath
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SimpleFinishLegalizing = false;
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@ -790,6 +780,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::MERGE_VALUES:
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case ISD::EH_RETURN:
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case ISD::FRAME_TO_ARGS_OFFSET:
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case ISD::EXCEPTIONADDR:
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case ISD::EHSELECTION:
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// These operations lie about being legal: when they claim to be legal,
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// they should actually be expanded.
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Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
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if (Action == TargetLowering::Legal)
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Action = TargetLowering::Expand;
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@ -797,6 +791,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::TRAMPOLINE:
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case ISD::FRAMEADDR:
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case ISD::RETURNADDR:
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// These operations lie about being legal: they must always be
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// custom-lowered.
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Action = TargetLowering::Custom;
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break;
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case ISD::BUILD_VECTOR:
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@ -2059,35 +2055,15 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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// Binary operators
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::MULHS:
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case ISD::MULHU:
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case ISD::UDIV:
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case ISD::SDIV:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FPOW:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
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if ((Node->getOpcode() == ISD::SHL ||
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Node->getOpcode() == ISD::SRL ||
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Node->getOpcode() == ISD::SRA) &&
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!Node->getValueType(0).isVector())
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Tmp2 = DAG.getShiftAmountOperand(Tmp2);
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Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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@ -2189,14 +2165,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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else if (VT == MVT::i128)
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LC = RTLIB::MUL_I128;
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break;
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case ISD::FPOW:
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LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
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RTLIB::POW_PPCF128);
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break;
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case ISD::FDIV:
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LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
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RTLIB::DIV_PPCF128);
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break;
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default: break;
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}
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if (LC != RTLIB::UNKNOWN_LIBCALL) {
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@ -2207,25 +2175,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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assert(0 && "Cannot expand this binary operator!");
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break;
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}
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case TargetLowering::Promote: {
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switch (Node->getOpcode()) {
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default: assert(0 && "Do not know how to promote this BinOp!");
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR: {
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MVT OVT = Node->getValueType(0);
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MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
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assert(OVT.isVector() && "Cannot promote this BinOp!");
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// Bit convert each of the values to the new type.
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Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
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Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
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Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
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// Bit convert the result back the original type.
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Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
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break;
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}
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}
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}
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}
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break;
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case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
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@ -2309,7 +2258,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case ISD::UREM:
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case ISD::SREM:
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case ISD::FREM:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
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@ -2369,11 +2317,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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else if (VT == MVT::i128)
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LC = (isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128);
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break;
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case ISD::FREM:
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// Floating point mod -> fmod libcall.
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LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
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RTLIB::REM_F80, RTLIB::REM_PPCF128);
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break;
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}
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if (LC != RTLIB::UNKNOWN_LIBCALL) {
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@ -2431,146 +2374,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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AddLegalizedOperand(SDValue(Node, 0), Result);
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AddLegalizedOperand(SDValue(Node, 1), Tmp1);
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return Op.getResNo() ? Tmp1 : Result;
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}
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// Unary operators
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case ISD::FABS:
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case ISD::FNEG:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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Tmp1 = LegalizeOp(Node->getOperand(0));
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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case TargetLowering::Promote:
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Result = DAG.UpdateNodeOperands(Result, Tmp1);
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if (isCustom) {
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.getNode()) Result = Tmp1;
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}
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break;
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case TargetLowering::Expand:
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FNEG:
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// Expand Y = FNEG(X) -> Y = SUB -0.0, X
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Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
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Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
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break;
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case ISD::FABS: {
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// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
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MVT VT = Node->getValueType(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
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Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
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break;
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}
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FEXP:
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case ISD::FEXP2:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT: {
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MVT VT = Node->getValueType(0);
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assert(!VT.isVector() && "Vector shouldn't get here!");
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch(Node->getOpcode()) {
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case ISD::FSQRT:
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LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
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RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
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break;
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case ISD::FSIN:
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LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
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break;
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case ISD::FCOS:
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LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_PPCF128);
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break;
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case ISD::FLOG:
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LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
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RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
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break;
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case ISD::FLOG2:
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LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
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RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
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break;
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case ISD::FLOG10:
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LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
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RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
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break;
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case ISD::FEXP:
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LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
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RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
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break;
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case ISD::FEXP2:
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LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
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RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
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break;
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case ISD::FTRUNC:
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LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
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RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
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break;
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case ISD::FFLOOR:
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LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
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RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
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break;
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case ISD::FCEIL:
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LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
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RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
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break;
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case ISD::FRINT:
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LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
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RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
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break;
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case ISD::FNEARBYINT:
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LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
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RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
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break;
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break;
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default: assert(0 && "Unreachable!");
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}
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Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/);
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break;
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}
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}
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break;
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}
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break;
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case ISD::FPOWI: {
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MVT VT = Node->getValueType(0);
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// Expand unsupported unary vector operators by unrolling them.
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assert(!VT.isVector() && "Vector shouldn't get here!");
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// We always lower FPOWI into a libcall. No target support for it yet.
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RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
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RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
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Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/);
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break;
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}
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case ISD::SADDO:
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case ISD::SSUBO: {
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@ -3025,6 +2828,38 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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return CallInfo.first;
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}
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SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
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RTLIB::Libcall Call_F32,
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RTLIB::Libcall Call_F64,
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RTLIB::Libcall Call_F80,
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RTLIB::Libcall Call_PPCF128) {
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT()) {
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default: assert(0 && "Unexpected request for libcall!");
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case MVT::f32: LC = Call_F32; break;
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case MVT::f64: LC = Call_F64; break;
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case MVT::f80: LC = Call_F80; break;
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case MVT::ppcf128: LC = Call_PPCF128; break;
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}
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return ExpandLibCall(LC, Node, false);
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}
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SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
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RTLIB::Libcall Call_I16,
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RTLIB::Libcall Call_I32,
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RTLIB::Libcall Call_I64,
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RTLIB::Libcall Call_I128) {
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT()) {
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default: assert(0 && "Unexpected request for libcall!");
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case MVT::i16: LC = Call_I16; break;
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case MVT::i32: LC = Call_I32; break;
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case MVT::i64: LC = Call_I64; break;
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case MVT::i128: LC = Call_I128; break;
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}
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return ExpandLibCall(LC, Node, isSigned);
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}
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/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
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/// INT_TO_FP operation of the specified operand when the target requests that
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/// we expand it. At this point, we know that the result and operand types are
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@ -3375,7 +3210,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
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void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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DebugLoc dl = Node->getDebugLoc();
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SDValue Tmp1, Tmp2;
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SDValue Tmp1, Tmp2, Tmp3;
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switch (Node->getOpcode()) {
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case ISD::CTPOP:
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case ISD::CTLZ:
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@ -3563,6 +3398,95 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(Node->getOperand(0));
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}
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break;
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case ISD::FNEG:
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// Expand Y = FNEG(X) -> Y = SUB -0.0, X
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Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
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Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
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Node->getOperand(0));
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Results.push_back(Tmp1);
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break;
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case ISD::FABS: {
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// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
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MVT VT = Node->getValueType(0);
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Tmp1 = Node->getOperand(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
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Results.push_back(Tmp1);
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break;
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}
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case ISD::FSQRT:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
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RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
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break;
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case ISD::FSIN:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
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break;
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case ISD::FCOS:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
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||||
RTLIB::COS_F80, RTLIB::COS_PPCF128));
|
||||
break;
|
||||
case ISD::FLOG:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
|
||||
RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
|
||||
break;
|
||||
case ISD::FLOG2:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
|
||||
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
|
||||
break;
|
||||
case ISD::FLOG10:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
|
||||
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
|
||||
break;
|
||||
case ISD::FEXP:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
|
||||
RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
|
||||
break;
|
||||
case ISD::FEXP2:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
|
||||
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
|
||||
break;
|
||||
case ISD::FTRUNC:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
|
||||
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
|
||||
break;
|
||||
case ISD::FFLOOR:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
|
||||
RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
|
||||
break;
|
||||
case ISD::FCEIL:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
|
||||
RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
|
||||
break;
|
||||
case ISD::FRINT:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
|
||||
RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
|
||||
break;
|
||||
case ISD::FNEARBYINT:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
|
||||
RTLIB::NEARBYINT_F64,
|
||||
RTLIB::NEARBYINT_F80,
|
||||
RTLIB::NEARBYINT_PPCF128));
|
||||
break;
|
||||
case ISD::FPOWI:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
|
||||
RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
|
||||
break;
|
||||
case ISD::FPOW:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
|
||||
RTLIB::POW_F80, RTLIB::POW_PPCF128));
|
||||
break;
|
||||
case ISD::FDIV:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
|
||||
RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
|
||||
break;
|
||||
case ISD::FREM:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
|
||||
RTLIB::REM_F80, RTLIB::REM_PPCF128));
|
||||
break;
|
||||
case ISD::GLOBAL_OFFSET_TABLE:
|
||||
case ISD::GlobalAddress:
|
||||
case ISD::GlobalTLSAddress:
|
||||
@ -3632,6 +3556,17 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
|
||||
Node->getOpcode() == ISD::SINT_TO_FP, dl);
|
||||
Results.push_back(Tmp1);
|
||||
break;
|
||||
case ISD::AND:
|
||||
case ISD::OR:
|
||||
case ISD::XOR:
|
||||
assert(OVT.isVector() && "Don't know how to promote scalar logic ops");
|
||||
// Bit convert each of the values to the new type.
|
||||
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
|
||||
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
|
||||
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
|
||||
// Bit convert the result back the original type.
|
||||
Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user