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1. In Thumb mode, select tBx instead of ARM variants.

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2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-14 01:49:27 +00:00
parent 0df6e09d43
commit f6bc4ae4a1
2 changed files with 16 additions and 20 deletions
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6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -617,7 +617,6 @@ let isCall = 1, Itinerary = IIC_Br,
let Inst{27-20} = 0b00010010; let Inst{27-20} = 0b00010010;
} }
let Uses = [LR] in {
// ARMv4T // ARMv4T
def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops), def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
"mov lr, pc\n\tbx $func", "mov lr, pc\n\tbx $func",
@ -627,7 +626,6 @@ let isCall = 1, Itinerary = IIC_Br,
let Inst{27-20} = 0b00010010; let Inst{27-20} = 0b00010010;
} }
} }
}
// On Darwin R9 is call-clobbered. // On Darwin R9 is call-clobbered.
let isCall = 1, Itinerary = IIC_Br, let isCall = 1, Itinerary = IIC_Br,
@ -650,17 +648,15 @@ let isCall = 1, Itinerary = IIC_Br,
let Inst{27-20} = 0b00010010; let Inst{27-20} = 0b00010010;
} }
let Uses = [LR] in {
// ARMv4T // ARMv4T
def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops), def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
"mov lr, pc\n\tbx $func", "mov lr, pc\n\tbx $func",
[(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]> { [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
let Inst{7-4} = 0b0001; let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111; let Inst{19-8} = 0b111111111111;
let Inst{27-20} = 0b00010010; let Inst{27-20} = 0b00010010;
} }
} }
}
let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in { let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
// B is "predicable" since it can be xformed into a Bcc. // B is "predicable" since it can be xformed into a Bcc.

4
lib/Target/ARM/ARMInstrThumb.td
View File

@ -180,7 +180,7 @@ let isCall = 1,
[(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>; [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
// ARMv4T // ARMv4T
def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops), def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
"cpy lr, pc\n\tbx $func", "mov lr, pc\n\tbx $func",
[(ARMcall_nolink tGPR:$func)]>; [(ARMcall_nolink tGPR:$func)]>;
} }
@ -196,7 +196,7 @@ let isBranch = 1, isTerminator = 1 in {
def tBR_JTr : T1JTI<(outs), def tBR_JTr : T1JTI<(outs),
(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
"cpy pc, $target \n\t.align\t2\n$jt", "mov pc, $target \n\t.align\t2\n$jt",
[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>; [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
} }
} }