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1. In Thumb mode, select tBx instead of ARM variants.
2. BX does not "use" the link register, it defines it. 3. Fix a couple more places in thumb td file that still uses pre-UAL syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75585 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -617,15 +617,13 @@ let isCall = 1, Itinerary = IIC_Br,
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let Inst{27-20} = 0b00010010;
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}
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let Uses = [LR] in {
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// ARMv4T
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def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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}
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// ARMv4T
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def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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}
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}
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@ -650,15 +648,13 @@ let isCall = 1, Itinerary = IIC_Br,
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let Inst{27-20} = 0b00010010;
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}
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let Uses = [LR] in {
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// ARMv4T
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def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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}
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// ARMv4T
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def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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}
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}
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@ -180,7 +180,7 @@ let isCall = 1,
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[(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
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// ARMv4T
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def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
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"cpy lr, pc\n\tbx $func",
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink tGPR:$func)]>;
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}
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@ -196,7 +196,7 @@ let isBranch = 1, isTerminator = 1 in {
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def tBR_JTr : T1JTI<(outs),
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(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
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"cpy pc, $target \n\t.align\t2\n$jt",
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"mov pc, $target \n\t.align\t2\n$jt",
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
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}
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}
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