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Handle REG_SEQUENCE with implicitly defined operands.
Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -125,8 +125,14 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg());
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vi.removeKill(MI);
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}
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unsigned Reg = MI->getOperand(0).getReg();
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MI->eraseFromParent();
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Changed = true;
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// A REG_SEQUENCE may have been expanded into partial definitions.
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// If this was the last one, mark Reg as implicitly defined.
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if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg))
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ImpDefRegs.insert(Reg);
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continue;
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}
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}
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@ -27,3 +27,24 @@ bb3:
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exit:
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ret void
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}
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; PR10520 - REG_SEQUENCE with implicit-def operands.
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define arm_aapcs_vfpcc void @foo() nounwind align 2 {
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bb:
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%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1>
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%tmp8 = bitcast <1 x i64> %tmp to <2 x float>
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%tmp9 = shufflevector <2 x float> %tmp8, <2 x float> %tmp8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%tmp10 = fmul <4 x float> undef, %tmp9
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%tmp11 = fadd <4 x float> %tmp10, undef
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%tmp12 = fadd <4 x float> undef, %tmp11
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%tmp13 = bitcast <4 x float> %tmp12 to i128
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%tmp14 = bitcast i128 %tmp13 to <4 x float>
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%tmp15 = bitcast <4 x float> %tmp14 to i128
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%tmp16 = bitcast i128 %tmp15 to <4 x float>
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%tmp17 = bitcast <4 x float> %tmp16 to i128
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%tmp18 = bitcast i128 %tmp17 to <4 x float>
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%tmp19 = bitcast <4 x float> %tmp18 to i128
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%tmp20 = bitcast i128 %tmp19 to <4 x float>
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store <4 x float> %tmp20, <4 x float>* undef, align 16
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ret void
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}
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