From f6cfc7d588df0c4833b5846896d1dd19e8d691d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dami=C3=A1n=20Silvani?= Date: Mon, 3 Aug 2015 20:10:07 -0300 Subject: [PATCH] Replace namespace SP for M6502 --- .../Mos6502/AsmParser/Mos6502AsmParser.cpp | 26 +- lib/Target/Mos6502/DelaySlotFiller.cpp | 100 +++---- .../Disassembler/Mos6502Disassembler.cpp | 82 +++--- .../InstPrinter/Mos6502InstPrinter.cpp | 58 ++--- .../MCTargetDesc/Mos6502MCCodeEmitter.cpp | 12 +- .../MCTargetDesc/Mos6502MCTargetDesc.cpp | 4 +- lib/Target/Mos6502/Mos6502AsmPrinter.cpp | 38 +-- lib/Target/Mos6502/Mos6502FrameLowering.cpp | 66 ++--- lib/Target/Mos6502/Mos6502ISelDAGToDAG.cpp | 12 +- lib/Target/Mos6502/Mos6502ISelLowering.cpp | 244 +++++++++--------- lib/Target/Mos6502/Mos6502InstrFormats.td | 2 +- lib/Target/Mos6502/Mos6502InstrInfo.cpp | 132 +++++----- lib/Target/Mos6502/Mos6502RegisterInfo.cpp | 70 ++--- lib/Target/Mos6502/Mos6502RegisterInfo.td | 20 +- 14 files changed, 433 insertions(+), 433 deletions(-) diff --git a/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp b/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp index 21d53c7e689..b2a7c1ae52e 100644 --- a/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp +++ b/lib/Target/Mos6502/AsmParser/Mos6502AsmParser.cpp @@ -23,10 +23,10 @@ using namespace llvm; // The generated AsmMatcher Mos6502GenAsmMatcher uses "Mos6502" as the target -// namespace. But MOS6502 backend uses "SP" as its namespace. +// namespace. But MOS6502 backend uses "M6502" as its namespace. namespace llvm { namespace Mos6502 { - using namespace SP; + using namespace M6502; } } @@ -131,14 +131,14 @@ public: Mos6502::Q12, Mos6502::Q13, Mos6502::Q14, Mos6502::Q15 }; static unsigned ASRRegs[32] = { - SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, - SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, - SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, - SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, - SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, - SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, - SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, - SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; + M6502::Y, M6502::ASR1, M6502::ASR2, M6502::ASR3, + M6502::ASR4, M6502::ASR5, M6502::ASR6, M6502::ASR7, + M6502::ASR8, M6502::ASR9, M6502::ASR10, M6502::ASR11, + M6502::ASR12, M6502::ASR13, M6502::ASR14, M6502::ASR15, + M6502::ASR16, M6502::ASR17, M6502::ASR18, M6502::ASR19, + M6502::ASR20, M6502::ASR21, M6502::ASR22, M6502::ASR23, + M6502::ASR24, M6502::ASR25, M6502::ASR26, M6502::ASR27, + M6502::ASR28, M6502::ASR29, M6502::ASR30, M6502::ASR31}; /// Mos6502Operand - Instances of this class represent a parsed Mos6502 machine /// instruction. @@ -421,7 +421,7 @@ void Mos6502AsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, const MCExpr *Expr = Mos6502MCExpr::create(Mos6502MCExpr::VK_Mos6502_HI, ValExpr, getContext()); TmpInst.setLoc(IDLoc); - TmpInst.setOpcode(SP::SETHIi); + TmpInst.setOpcode(M6502::SETHIi); TmpInst.addOperand(MCRegOp); TmpInst.addOperand(MCOperand::createExpr(Expr)); Instructions.push_back(TmpInst); @@ -433,7 +433,7 @@ void Mos6502AsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, const MCExpr *Expr = Mos6502MCExpr::create(Mos6502MCExpr::VK_Mos6502_LO, ValExpr, getContext()); TmpInst.setLoc(IDLoc); - TmpInst.setOpcode(SP::ORri); + TmpInst.setOpcode(M6502::ORri); TmpInst.addOperand(MCRegOp); TmpInst.addOperand(PrevReg); TmpInst.addOperand(MCOperand::createExpr(Expr)); @@ -457,7 +457,7 @@ bool Mos6502AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, Inst.setLoc(IDLoc); Instructions.push_back(Inst); break; - case SP::SET: + case M6502::SET: expandSET(Inst, IDLoc, Instructions); break; } diff --git a/lib/Target/Mos6502/DelaySlotFiller.cpp b/lib/Target/Mos6502/DelaySlotFiller.cpp index 7c688bc0aaf..8eec2b51c36 100644 --- a/lib/Target/Mos6502/DelaySlotFiller.cpp +++ b/lib/Target/Mos6502/DelaySlotFiller.cpp @@ -116,16 +116,16 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { // If MI is restore, try combining it with previous inst. if (!DisableDelaySlotFiller && - (MI->getOpcode() == SP::RESTORErr - || MI->getOpcode() == SP::RESTOREri)) { + (MI->getOpcode() == M6502::RESTORErr + || MI->getOpcode() == M6502::RESTOREri)) { Changed |= tryCombineRestoreWithPrevInst(MBB, MI); continue; } if (!Subtarget->isV9() && - (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD - || MI->getOpcode() == SP::FCMPQ)) { - BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); + (MI->getOpcode() == M6502::FCMPS || MI->getOpcode() == M6502::FCMPD + || MI->getOpcode() == M6502::FCMPQ)) { + BuildMI(MBB, I, MI->getDebugLoc(), TII->get(M6502::NOP)); Changed = true; continue; } @@ -143,7 +143,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { Changed = true; if (D == MBB.end()) - BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); + BuildMI(MBB, I, MI->getDebugLoc(), TII->get(M6502::NOP)); else MBB.splice(I, &MBB, D); @@ -153,7 +153,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { ++J; // skip the delay filler. assert (J != MBB.end() && "MI needs a delay instruction."); BuildMI(MBB, ++J, MI->getDebugLoc(), - TII->get(SP::UNIMP)).addImm(structSize); + TII->get(M6502::UNIMP)).addImm(structSize); // Bundle the delay filler and unimp with the instruction. MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J); } else { @@ -175,17 +175,17 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (slot == MBB.begin()) return MBB.end(); - if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) + if (slot->getOpcode() == M6502::RET || slot->getOpcode() == M6502::TLS_CALL) return MBB.end(); - if (slot->getOpcode() == SP::RETL) { + if (slot->getOpcode() == M6502::RETL) { MachineBasicBlock::iterator J = slot; --J; - if (J->getOpcode() == SP::RESTORErr - || J->getOpcode() == SP::RESTOREri) { + if (J->getOpcode() == M6502::RESTORErr + || J->getOpcode() == M6502::RESTOREri) { // change retl to ret. - slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); + slot->setDesc(Subtarget->getInstrInfo()->get(M6502::RET)); return J; } } @@ -275,13 +275,13 @@ void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI, SmallSet& RegUses) { // Call defines o7, which is visible to the instruction in delay slot. - RegDefs.insert(SP::O7); + RegDefs.insert(M6502::O7); switch(MI->getOpcode()) { default: llvm_unreachable("Unknown opcode."); - case SP::CALL: break; - case SP::CALLrr: - case SP::CALLri: + case M6502::CALL: break; + case M6502::CALLrr: + case M6502::CALLri: assert(MI->getNumOperands() >= 2); const MachineOperand &Reg = MI->getOperand(0); assert(Reg.isReg() && "CALL first operand is not a register."); @@ -316,7 +316,7 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, if (MO.isUse()) { // Implicit register uses of retl are return values and // retl does not use them. - if (MO.isImplicit() && MI->getOpcode() == SP::RETL) + if (MO.isImplicit() && MI->getOpcode() == M6502::RETL) continue; RegUses.insert(Reg); } @@ -342,10 +342,10 @@ bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize) unsigned structSizeOpNum = 0; switch (I->getOpcode()) { default: llvm_unreachable("Unknown call opcode."); - case SP::CALL: structSizeOpNum = 1; break; - case SP::CALLrr: - case SP::CALLri: structSizeOpNum = 2; break; - case SP::TLS_CALL: return false; + case M6502::CALL: structSizeOpNum = 1; break; + case M6502::CALLrr: + case M6502::CALLri: structSizeOpNum = 2; break; + case M6502::TLS_CALL: return false; } const MachineOperand &MO = I->getOperand(structSizeOpNum); @@ -365,19 +365,19 @@ static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI, // After : restore , , %o[0-7] unsigned reg = AddMI->getOperand(0).getReg(); - if (reg < SP::I0 || reg > SP::I7) + if (reg < M6502::I0 || reg > M6502::I7) return false; // Erase RESTORE. RestoreMI->eraseFromParent(); // Change ADD to RESTORE. - AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) - ? SP::RESTORErr - : SP::RESTOREri)); + AddMI->setDesc(TII->get((AddMI->getOpcode() == M6502::ADDrr) + ? M6502::RESTORErr + : M6502::RESTOREri)); // Map the destination register. - AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); + AddMI->getOperand(0).setReg(reg - M6502::I0 + M6502::O0); return true; } @@ -393,17 +393,17 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI, // After : restore , , %o[0-7] unsigned reg = OrMI->getOperand(0).getReg(); - if (reg < SP::I0 || reg > SP::I7) + if (reg < M6502::I0 || reg > M6502::I7) return false; // check whether it is a copy. - if (OrMI->getOpcode() == SP::ORrr - && OrMI->getOperand(1).getReg() != SP::G0 - && OrMI->getOperand(2).getReg() != SP::G0) + if (OrMI->getOpcode() == M6502::ORrr + && OrMI->getOperand(1).getReg() != M6502::G0 + && OrMI->getOperand(2).getReg() != M6502::G0) return false; - if (OrMI->getOpcode() == SP::ORri - && OrMI->getOperand(1).getReg() != SP::G0 + if (OrMI->getOpcode() == M6502::ORri + && OrMI->getOperand(1).getReg() != M6502::G0 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0)) return false; @@ -411,12 +411,12 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI, RestoreMI->eraseFromParent(); // Change OR to RESTORE. - OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) - ? SP::RESTORErr - : SP::RESTOREri)); + OrMI->setDesc(TII->get((OrMI->getOpcode() == M6502::ORrr) + ? M6502::RESTORErr + : M6502::RESTOREri)); // Map the destination register. - OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); + OrMI->getOperand(0).setReg(reg - M6502::I0 + M6502::O0); return true; } @@ -431,7 +431,7 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, // After : restore %g0, (imm3<<10), %o[0-7] unsigned reg = SetHiMI->getOperand(0).getReg(); - if (reg < SP::I0 || reg > SP::I7) + if (reg < M6502::I0 || reg > M6502::I7) return false; if (!SetHiMI->getOperand(1).isImm()) @@ -446,12 +446,12 @@ static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, // Make it a 13 bit immediate. imm = (imm << 10) & 0x1FFF; - assert(RestoreMI->getOpcode() == SP::RESTORErr); + assert(RestoreMI->getOpcode() == M6502::RESTORErr); - RestoreMI->setDesc(TII->get(SP::RESTOREri)); + RestoreMI->setDesc(TII->get(M6502::RESTOREri)); - RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); - RestoreMI->getOperand(1).setReg(SP::G0); + RestoreMI->getOperand(0).setReg(reg - M6502::I0 + M6502::O0); + RestoreMI->getOperand(1).setReg(M6502::G0); RestoreMI->getOperand(2).ChangeToImmediate(imm); @@ -469,10 +469,10 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, return false; // assert that MBBI is a "restore %g0, %g0, %g0". - assert(MBBI->getOpcode() == SP::RESTORErr - && MBBI->getOperand(0).getReg() == SP::G0 - && MBBI->getOperand(1).getReg() == SP::G0 - && MBBI->getOperand(2).getReg() == SP::G0); + assert(MBBI->getOpcode() == M6502::RESTORErr + && MBBI->getOperand(0).getReg() == M6502::G0 + && MBBI->getOperand(1).getReg() == M6502::G0 + && MBBI->getOperand(2).getReg() == M6502::G0); MachineBasicBlock::iterator PrevInst = std::prev(MBBI); @@ -484,11 +484,11 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, switch (PrevInst->getOpcode()) { default: break; - case SP::ADDrr: - case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; - case SP::ORrr: - case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break; - case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break; + case M6502::ADDrr: + case M6502::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; + case M6502::ORrr: + case M6502::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break; + case M6502::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break; } // It cannot combine with the previous instruction. return false; diff --git a/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp b/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp index 94cd6f1d7ad..1798bfe5e3d 100644 --- a/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp +++ b/lib/Target/Mos6502/Disassembler/Mos6502Disassembler.cpp @@ -61,57 +61,57 @@ extern "C" void LLVMInitializeMos6502Disassembler() { } static const unsigned IntRegDecoderTable[] = { - SP::G0, SP::G1, SP::G2, SP::G3, - SP::G4, SP::G5, SP::G6, SP::G7, - SP::O0, SP::O1, SP::O2, SP::O3, - SP::O4, SP::O5, SP::O6, SP::O7, - SP::L0, SP::L1, SP::L2, SP::L3, - SP::L4, SP::L5, SP::L6, SP::L7, - SP::I0, SP::I1, SP::I2, SP::I3, - SP::I4, SP::I5, SP::I6, SP::I7 }; + M6502::G0, M6502::G1, M6502::G2, M6502::G3, + M6502::G4, M6502::G5, M6502::G6, M6502::G7, + M6502::O0, M6502::O1, M6502::O2, M6502::O3, + M6502::O4, M6502::O5, M6502::O6, M6502::O7, + M6502::L0, M6502::L1, M6502::L2, M6502::L3, + M6502::L4, M6502::L5, M6502::L6, M6502::L7, + M6502::I0, M6502::I1, M6502::I2, M6502::I3, + M6502::I4, M6502::I5, M6502::I6, M6502::I7 }; static const unsigned FPRegDecoderTable[] = { - SP::F0, SP::F1, SP::F2, SP::F3, - SP::F4, SP::F5, SP::F6, SP::F7, - SP::F8, SP::F9, SP::F10, SP::F11, - SP::F12, SP::F13, SP::F14, SP::F15, - SP::F16, SP::F17, SP::F18, SP::F19, - SP::F20, SP::F21, SP::F22, SP::F23, - SP::F24, SP::F25, SP::F26, SP::F27, - SP::F28, SP::F29, SP::F30, SP::F31 }; + M6502::F0, M6502::F1, M6502::F2, M6502::F3, + M6502::F4, M6502::F5, M6502::F6, M6502::F7, + M6502::F8, M6502::F9, M6502::F10, M6502::F11, + M6502::F12, M6502::F13, M6502::F14, M6502::F15, + M6502::F16, M6502::F17, M6502::F18, M6502::F19, + M6502::F20, M6502::F21, M6502::F22, M6502::F23, + M6502::F24, M6502::F25, M6502::F26, M6502::F27, + M6502::F28, M6502::F29, M6502::F30, M6502::F31 }; static const unsigned DFPRegDecoderTable[] = { - SP::D0, SP::D16, SP::D1, SP::D17, - SP::D2, SP::D18, SP::D3, SP::D19, - SP::D4, SP::D20, SP::D5, SP::D21, - SP::D6, SP::D22, SP::D7, SP::D23, - SP::D8, SP::D24, SP::D9, SP::D25, - SP::D10, SP::D26, SP::D11, SP::D27, - SP::D12, SP::D28, SP::D13, SP::D29, - SP::D14, SP::D30, SP::D15, SP::D31 }; + M6502::D0, M6502::D16, M6502::D1, M6502::D17, + M6502::D2, M6502::D18, M6502::D3, M6502::D19, + M6502::D4, M6502::D20, M6502::D5, M6502::D21, + M6502::D6, M6502::D22, M6502::D7, M6502::D23, + M6502::D8, M6502::D24, M6502::D9, M6502::D25, + M6502::D10, M6502::D26, M6502::D11, M6502::D27, + M6502::D12, M6502::D28, M6502::D13, M6502::D29, + M6502::D14, M6502::D30, M6502::D15, M6502::D31 }; static const unsigned QFPRegDecoderTable[] = { - SP::Q0, SP::Q8, ~0U, ~0U, - SP::Q1, SP::Q9, ~0U, ~0U, - SP::Q2, SP::Q10, ~0U, ~0U, - SP::Q3, SP::Q11, ~0U, ~0U, - SP::Q4, SP::Q12, ~0U, ~0U, - SP::Q5, SP::Q13, ~0U, ~0U, - SP::Q6, SP::Q14, ~0U, ~0U, - SP::Q7, SP::Q15, ~0U, ~0U } ; + M6502::Q0, M6502::Q8, ~0U, ~0U, + M6502::Q1, M6502::Q9, ~0U, ~0U, + M6502::Q2, M6502::Q10, ~0U, ~0U, + M6502::Q3, M6502::Q11, ~0U, ~0U, + M6502::Q4, M6502::Q12, ~0U, ~0U, + M6502::Q5, M6502::Q13, ~0U, ~0U, + M6502::Q6, M6502::Q14, ~0U, ~0U, + M6502::Q7, M6502::Q15, ~0U, ~0U } ; static const unsigned FCCRegDecoderTable[] = { - SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; + M6502::FCC0, M6502::FCC1, M6502::FCC2, M6502::FCC3 }; static const unsigned ASRRegDecoderTable[] = { - SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, - SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, - SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, - SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, - SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, - SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, - SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, - SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; + M6502::Y, M6502::ASR1, M6502::ASR2, M6502::ASR3, + M6502::ASR4, M6502::ASR5, M6502::ASR6, M6502::ASR7, + M6502::ASR8, M6502::ASR9, M6502::ASR10, M6502::ASR11, + M6502::ASR12, M6502::ASR13, M6502::ASR14, M6502::ASR15, + M6502::ASR16, M6502::ASR17, M6502::ASR18, M6502::ASR19, + M6502::ASR20, M6502::ASR21, M6502::ASR22, M6502::ASR23, + M6502::ASR24, M6502::ASR25, M6502::ASR26, M6502::ASR27, + M6502::ASR28, M6502::ASR29, M6502::ASR30, M6502::ASR31}; static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, diff --git a/lib/Target/Mos6502/InstPrinter/Mos6502InstPrinter.cpp b/lib/Target/Mos6502/InstPrinter/Mos6502InstPrinter.cpp index a7f0de07c67..075a26abe0d 100644 --- a/lib/Target/Mos6502/InstPrinter/Mos6502InstPrinter.cpp +++ b/lib/Target/Mos6502/InstPrinter/Mos6502InstPrinter.cpp @@ -23,10 +23,10 @@ using namespace llvm; #define DEBUG_TYPE "asm-printer" // The generated AsmMatcher Mos6502GenAsmWriter uses "Mos6502" as the target -// namespace. But MOS6502 backend uses "SP" as its namespace. +// namespace. But MOS6502 backend uses "M6502" as its namespace. namespace llvm { namespace Mos6502 { - using namespace SP; + using namespace M6502; } } @@ -55,46 +55,46 @@ bool Mos6502InstPrinter::printMos6502AliasInstr(const MCInst *MI, raw_ostream &O) { switch (MI->getOpcode()) { default: return false; - case SP::JMPLrr: - case SP::JMPLri: { + case M6502::JMPLrr: + case M6502::JMPLri: { if (MI->getNumOperands() != 3) return false; if (!MI->getOperand(0).isReg()) return false; switch (MI->getOperand(0).getReg()) { default: return false; - case SP::G0: // jmp $addr | ret | retl + case M6502::G0: // jmp $addr | ret | retl if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 8) { switch(MI->getOperand(1).getReg()) { default: break; - case SP::I7: O << "\tret"; return true; - case SP::O7: O << "\tretl"; return true; + case M6502::I7: O << "\tret"; return true; + case M6502::O7: O << "\tretl"; return true; } } O << "\tjmp "; printMemOperand(MI, 1, STI, O); return true; - case SP::O7: // call $addr + case M6502::O7: // call $addr O << "\tcall "; printMemOperand(MI, 1, STI, O); return true; } } - case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: - case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { + case M6502::V9FCMPS: case M6502::V9FCMPD: case M6502::V9FCMPQ: + case M6502::V9FCMPES: case M6502::V9FCMPED: case M6502::V9FCMPEQ: { if (isV9(STI) || (MI->getNumOperands() != 3) || (!MI->getOperand(0).isReg()) - || (MI->getOperand(0).getReg() != SP::FCC0)) + || (MI->getOperand(0).getReg() != M6502::FCC0)) return false; // if V8, skip printing %fcc0. switch(MI->getOpcode()) { default: - case SP::V9FCMPS: O << "\tfcmps "; break; - case SP::V9FCMPD: O << "\tfcmpd "; break; - case SP::V9FCMPQ: O << "\tfcmpq "; break; - case SP::V9FCMPES: O << "\tfcmpes "; break; - case SP::V9FCMPED: O << "\tfcmped "; break; - case SP::V9FCMPEQ: O << "\tfcmpeq "; break; + case M6502::V9FCMPS: O << "\tfcmps "; break; + case M6502::V9FCMPD: O << "\tfcmpd "; break; + case M6502::V9FCMPQ: O << "\tfcmpq "; break; + case M6502::V9FCMPES: O << "\tfcmpes "; break; + case M6502::V9FCMPED: O << "\tfcmped "; break; + case M6502::V9FCMPEQ: O << "\tfcmpeq "; break; } printOperand(MI, 1, STI, O); O << ", "; @@ -136,7 +136,7 @@ void Mos6502InstPrinter::printMemOperand(const MCInst *MI, int opNum, } const MCOperand &MO = MI->getOperand(opNum+1); - if (MO.isReg() && MO.getReg() == SP::G0) + if (MO.isReg() && MO.getReg() == M6502::G0) return; // don't print "+%g0" if (MO.isImm() && MO.getImm() == 0) return; // don't print "+0" @@ -152,17 +152,17 @@ void Mos6502InstPrinter::printCCOperand(const MCInst *MI, int opNum, int CC = (int)MI->getOperand(opNum).getImm(); switch (MI->getOpcode()) { default: break; - case SP::FBCOND: - case SP::FBCONDA: - case SP::BPFCC: - case SP::BPFCCA: - case SP::BPFCCNT: - case SP::BPFCCANT: - case SP::MOVFCCrr: case SP::V9MOVFCCrr: - case SP::MOVFCCri: case SP::V9MOVFCCri: - case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: - case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: - case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC: + case M6502::FBCOND: + case M6502::FBCONDA: + case M6502::BPFCC: + case M6502::BPFCCA: + case M6502::BPFCCNT: + case M6502::BPFCCANT: + case M6502::MOVFCCrr: case M6502::V9MOVFCCrr: + case M6502::MOVFCCri: case M6502::V9MOVFCCri: + case M6502::FMOVS_FCC: case M6502::V9FMOVS_FCC: + case M6502::FMOVD_FCC: case M6502::V9FMOVD_FCC: + case M6502::FMOVQ_FCC: case M6502::V9FMOVQ_FCC: // Make sure CC is a fp conditional flag. CC = (CC < 16) ? (CC + 16) : CC; break; diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCCodeEmitter.cpp b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCCodeEmitter.cpp index e904893077d..797c2e7cd11 100644 --- a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCCodeEmitter.cpp +++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCCodeEmitter.cpp @@ -94,11 +94,11 @@ void Mos6502MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, unsigned tlsOpNo = 0; switch (MI.getOpcode()) { default: break; - case SP::TLS_CALL: tlsOpNo = 1; break; - case SP::TLS_ADDrr: - case SP::TLS_ADDXrr: - case SP::TLS_LDrr: - case SP::TLS_LDXrr: tlsOpNo = 3; break; + case M6502::TLS_CALL: tlsOpNo = 1; break; + case M6502::TLS_ADDrr: + case M6502::TLS_ADDXrr: + case M6502::TLS_LDrr: + case M6502::TLS_LDXrr: tlsOpNo = 3; break; } if (tlsOpNo != 0) { const MCOperand &MO = MI.getOperand(tlsOpNo); @@ -146,7 +146,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - if (MI.getOpcode() == SP::TLS_CALL) { + if (MI.getOpcode() == M6502::TLS_CALL) { // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in // encodeInstruction. #ifndef NDEBUG diff --git a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp index 57fbf9ffd73..55ae09fe5fb 100644 --- a/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp +++ b/lib/Target/Mos6502/MCTargetDesc/Mos6502MCTargetDesc.cpp @@ -36,7 +36,7 @@ using namespace llvm; static MCAsmInfo *createMos6502MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT) { MCAsmInfo *MAI = new Mos6502ELFMCAsmInfo(TT); - unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); + unsigned Reg = MRI.getDwarfRegNum(M6502::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; @@ -50,7 +50,7 @@ static MCInstrInfo *createMos6502MCInstrInfo() { static MCRegisterInfo *createMos6502MCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); - InitMos6502MCRegisterInfo(X, SP::O7); + InitMos6502MCRegisterInfo(X, M6502::O7); return X; } diff --git a/lib/Target/Mos6502/Mos6502AsmPrinter.cpp b/lib/Target/Mos6502/Mos6502AsmPrinter.cpp index cd78041e6c5..516538ca97b 100644 --- a/lib/Target/Mos6502/Mos6502AsmPrinter.cpp +++ b/lib/Target/Mos6502/Mos6502AsmPrinter.cpp @@ -113,7 +113,7 @@ static void EmitCall(MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { MCInst CallInst; - CallInst.setOpcode(SP::CALL); + CallInst.setOpcode(M6502::CALL); CallInst.addOperand(Callee); OutStreamer.EmitInstruction(CallInst, STI); } @@ -123,7 +123,7 @@ static void EmitSETHI(MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { MCInst SETHIInst; - SETHIInst.setOpcode(SP::SETHIi); + SETHIInst.setOpcode(M6502::SETHIi); SETHIInst.addOperand(RD); SETHIInst.addOperand(Imm); OutStreamer.EmitInstruction(SETHIInst, STI); @@ -144,19 +144,19 @@ static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) { - EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); + EmitBinary(OutStreamer, M6502::ORri, RS1, Imm, RD, STI); } static void EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) { - EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI); + EmitBinary(OutStreamer, M6502::ADDrr, RS1, RS2, RD, STI); } static void EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) { - EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI); + EmitBinary(OutStreamer, M6502::SLLri, RS1, Imm, RD, STI); } @@ -180,7 +180,7 @@ void Mos6502AsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); const MachineOperand &MO = MI->getOperand(0); - assert(MO.getReg() != SP::O7 && + assert(MO.getReg() != M6502::O7 && "%o7 is assigned as destination for getpcx!"); MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); @@ -216,7 +216,7 @@ void Mos6502AsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, OutContext)); EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI); // Use register %o7 to load the lower 32 bits. - MCOperand RegO7 = MCOperand::createReg(SP::O7); + MCOperand RegO7 = MCOperand::createReg(M6502::O7); EmitHiLo(*OutStreamer, GOTLabel, Mos6502MCExpr::VK_Mos6502_HI, Mos6502MCExpr::VK_Mos6502_LO, RegO7, OutContext, STI); @@ -230,7 +230,7 @@ void Mos6502AsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, MCSymbol *EndLabel = OutContext.createTempSymbol(); MCSymbol *SethiLabel = OutContext.createTempSymbol(); - MCOperand RegO7 = MCOperand::createReg(SP::O7); + MCOperand RegO7 = MCOperand::createReg(M6502::O7); // : // call @@ -264,7 +264,7 @@ void Mos6502AsmPrinter::EmitInstruction(const MachineInstr *MI) case TargetOpcode::DBG_VALUE: // FIXME: Debug Value. return; - case SP::GETPCX: + case M6502::GETPCX: LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo()); return; } @@ -282,13 +282,13 @@ void Mos6502AsmPrinter::EmitFunctionBodyStart() { return; const MachineRegisterInfo &MRI = MF->getRegInfo(); - const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; + const unsigned globalRegs[] = { M6502::G2, M6502::G3, M6502::G6, M6502::G7, 0 }; for (unsigned i = 0; globalRegs[i] != 0; ++i) { unsigned reg = globalRegs[i]; if (MRI.use_empty(reg)) continue; - if (reg == SP::G6 || reg == SP::G7) + if (reg == M6502::G6 || reg == M6502::G7) getTargetStreamer().emitMos6502RegisterIgnore(reg); else getTargetStreamer().emitMos6502RegisterScratch(reg); @@ -304,10 +304,10 @@ void Mos6502AsmPrinter::printOperand(const MachineInstr *MI, int opNum, #ifndef NDEBUG // Verify the target flags. if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) { - if (MI->getOpcode() == SP::CALL) + if (MI->getOpcode() == M6502::CALL) assert(TF == Mos6502MCExpr::VK_Mos6502_None && "Cannot handle target flags on call address"); - else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) + else if (MI->getOpcode() == M6502::SETHIi || MI->getOpcode() == M6502::SETHIXi) assert((TF == Mos6502MCExpr::VK_Mos6502_HI || TF == Mos6502MCExpr::VK_Mos6502_H44 || TF == Mos6502MCExpr::VK_Mos6502_HH @@ -317,24 +317,24 @@ void Mos6502AsmPrinter::printOperand(const MachineInstr *MI, int opNum, || TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_HI22 || TF == Mos6502MCExpr::VK_Mos6502_TLS_LE_HIX22) && "Invalid target flags for address operand on sethi"); - else if (MI->getOpcode() == SP::TLS_CALL) + else if (MI->getOpcode() == M6502::TLS_CALL) assert((TF == Mos6502MCExpr::VK_Mos6502_None || TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_CALL || TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_CALL) && "Cannot handle target flags on tls call address"); - else if (MI->getOpcode() == SP::TLS_ADDrr) + else if (MI->getOpcode() == M6502::TLS_ADDrr) assert((TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_ADD || TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_ADD || TF == Mos6502MCExpr::VK_Mos6502_TLS_LDO_ADD || TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_ADD) && "Cannot handle target flags on add for TLS"); - else if (MI->getOpcode() == SP::TLS_LDrr) + else if (MI->getOpcode() == M6502::TLS_LDrr) assert(TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_LD && "Cannot handle target flags on ld for TLS"); - else if (MI->getOpcode() == SP::TLS_LDXrr) + else if (MI->getOpcode() == M6502::TLS_LDXrr) assert(TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_LDX && "Cannot handle target flags on ldx for TLS"); - else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri) + else if (MI->getOpcode() == M6502::XORri || MI->getOpcode() == M6502::XORXri) assert((TF == Mos6502MCExpr::VK_Mos6502_TLS_LDO_LOX10 || TF == Mos6502MCExpr::VK_Mos6502_TLS_LE_LOX10) && "Cannot handle target flags on xor for TLS"); @@ -395,7 +395,7 @@ void Mos6502AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, } if (MI->getOperand(opNum+1).isReg() && - MI->getOperand(opNum+1).getReg() == SP::G0) + MI->getOperand(opNum+1).getReg() == M6502::G0) return; // don't print "+%g0" if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) diff --git a/lib/Target/Mos6502/Mos6502FrameLowering.cpp b/lib/Target/Mos6502/Mos6502FrameLowering.cpp index cb9fb0be45d..00a99892fbb 100644 --- a/lib/Target/Mos6502/Mos6502FrameLowering.cpp +++ b/lib/Target/Mos6502/Mos6502FrameLowering.cpp @@ -49,8 +49,8 @@ void Mos6502FrameLowering::emitSPAdjustment(MachineFunction &MF, *static_cast(MF.getSubtarget().getInstrInfo()); if (NumBytes >= -4096 && NumBytes < 4096) { - BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) - .addReg(SP::O6).addImm(NumBytes); + BuildMI(MBB, MBBI, dl, TII.get(ADDri), M6502::O6) + .addReg(M6502::O6).addImm(NumBytes); return; } @@ -61,12 +61,12 @@ void Mos6502FrameLowering::emitSPAdjustment(MachineFunction &MF, // sethi %hi(NumBytes), %g1 // or %g1, %lo(NumBytes), %g1 // add %sp, %g1, %sp - BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) + BuildMI(MBB, MBBI, dl, TII.get(M6502::SETHIi), M6502::G1) .addImm(HI22(NumBytes)); - BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) - .addReg(SP::G1).addImm(LO10(NumBytes)); - BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) - .addReg(SP::O6).addReg(SP::G1); + BuildMI(MBB, MBBI, dl, TII.get(M6502::ORri), M6502::G1) + .addReg(M6502::G1).addImm(LO10(NumBytes)); + BuildMI(MBB, MBBI, dl, TII.get(ADDrr), M6502::O6) + .addReg(M6502::O6).addReg(M6502::G1); return ; } @@ -74,12 +74,12 @@ void Mos6502FrameLowering::emitSPAdjustment(MachineFunction &MF, // sethi %hix(NumBytes), %g1 // xor %g1, %lox(NumBytes), %g1 // add %sp, %g1, %sp - BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) + BuildMI(MBB, MBBI, dl, TII.get(M6502::SETHIi), M6502::G1) .addImm(HIX22(NumBytes)); - BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) - .addReg(SP::G1).addImm(LOX10(NumBytes)); - BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) - .addReg(SP::O6).addReg(SP::G1); + BuildMI(MBB, MBBI, dl, TII.get(M6502::XORri), M6502::G1) + .addReg(M6502::G1).addImm(LOX10(NumBytes)); + BuildMI(MBB, MBBI, dl, TII.get(ADDrr), M6502::O6) + .addReg(M6502::O6).addReg(M6502::G1); } void Mos6502FrameLowering::emitPrologue(MachineFunction &MF, @@ -96,20 +96,20 @@ void Mos6502FrameLowering::emitPrologue(MachineFunction &MF, // Get the number of bytes to allocate from the FrameInfo int NumBytes = (int) MFI->getStackSize(); - unsigned SAVEri = SP::SAVEri; - unsigned SAVErr = SP::SAVErr; + unsigned SAVEri = M6502::SAVEri; + unsigned SAVErr = M6502::SAVErr; if (FuncInfo->isLeafProc()) { if (NumBytes == 0) return; - SAVEri = SP::ADDri; - SAVErr = SP::ADDrr; + SAVEri = M6502::ADDri; + SAVErr = M6502::ADDrr; } NumBytes = -MF.getSubtarget().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - unsigned regFP = MRI->getDwarfRegNum(SP::I6, true); + unsigned regFP = MRI->getDwarfRegNum(M6502::I6, true); // Emit ".cfi_def_cfa_register 30". unsigned CFIIndex = @@ -122,8 +122,8 @@ void Mos6502FrameLowering::emitPrologue(MachineFunction &MF, BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); - unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true); - unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true); + unsigned regInRA = MRI->getDwarfRegNum(M6502::I7, true); + unsigned regOutRA = MRI->getDwarfRegNum(M6502::O7, true); // Emit ".cfi_register 15, 31". CFIIndex = MMI.addFrameInst( MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); @@ -137,11 +137,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, if (!hasReservedCallFrame(MF)) { MachineInstr &MI = *I; int Size = MI.getOperand(0).getImm(); - if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) + if (MI.getOpcode() == M6502::ADJCALLSTACKDOWN) Size = -Size; if (Size) - emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); + emitSPAdjustment(MF, MBB, I, Size, M6502::ADDrr, M6502::ADDri); } MBB.erase(I); } @@ -154,11 +154,11 @@ void Mos6502FrameLowering::emitEpilogue(MachineFunction &MF, const Mos6502InstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); - assert(MBBI->getOpcode() == SP::RETL && + assert(MBBI->getOpcode() == M6502::RETL && "Can only put epilog before 'retl' instruction!"); if (!FuncInfo->isLeafProc()) { - BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) - .addReg(SP::G0); + BuildMI(MBB, MBBI, dl, TII.get(M6502::RESTORErr), M6502::G0).addReg(M6502::G0) + .addReg(M6502::G0); return; } MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -168,7 +168,7 @@ void Mos6502FrameLowering::emitEpilogue(MachineFunction &MF, return; NumBytes = MF.getSubtarget().getAdjustedFrameSize(NumBytes); - emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); + emitSPAdjustment(MF, MBB, MBBI, NumBytes, M6502::ADDrr, M6502::ADDri); } bool Mos6502FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { @@ -189,11 +189,11 @@ bool Mos6502FrameLowering::hasFP(const MachineFunction &MF) const { static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) { - for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) + for (unsigned reg = M6502::I0; reg <= M6502::I7; ++reg) if (!MRI->reg_nodbg_empty(reg)) return false; - for (unsigned reg = SP::L0; reg <= SP::L7; ++reg) + for (unsigned reg = M6502::L0; reg <= M6502::L7; ++reg) if (!MRI->reg_nodbg_empty(reg)) return false; @@ -207,8 +207,8 @@ bool Mos6502FrameLowering::isLeafProc(MachineFunction &MF) const MachineFrameInfo *MFI = MF.getFrameInfo(); return !(MFI->hasCalls() // has calls - || !MRI.reg_nodbg_empty(SP::L0) // Too many registers needed - || !MRI.reg_nodbg_empty(SP::O6) // %SP is used + || !MRI.reg_nodbg_empty(M6502::L0) // Too many registers needed + || !MRI.reg_nodbg_empty(M6502::O6) // %SP is used || hasFP(MF)); // need %FP } @@ -217,10 +217,10 @@ void Mos6502FrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { MachineRegisterInfo &MRI = MF.getRegInfo(); // Remap %i[0-7] to %o[0-7]. - for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { + for (unsigned reg = M6502::I0; reg <= M6502::I7; ++reg) { if (MRI.reg_nodbg_empty(reg)) continue; - unsigned mapped_reg = (reg - SP::I0 + SP::O0); + unsigned mapped_reg = (reg - M6502::I0 + M6502::O0); assert(MRI.reg_nodbg_empty(mapped_reg)); // Replace I register with O register. @@ -230,11 +230,11 @@ void Mos6502FrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { // Rewrite MBB's Live-ins. for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); MBB != E; ++MBB) { - for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { + for (unsigned reg = M6502::I0; reg <= M6502::I7; ++reg) { if (!MBB->isLiveIn(reg)) continue; MBB->removeLiveIn(reg); - MBB->addLiveIn(reg - SP::I0 + SP::O0); + MBB->addLiveIn(reg - M6502::I0 + M6502::O0); } } diff --git a/lib/Target/Mos6502/Mos6502ISelDAGToDAG.cpp b/lib/Target/Mos6502/Mos6502ISelDAGToDAG.cpp index 26397d09c7e..626c06d9991 100644 --- a/lib/Target/Mos6502/Mos6502ISelDAGToDAG.cpp +++ b/lib/Target/Mos6502/Mos6502ISelDAGToDAG.cpp @@ -137,7 +137,7 @@ bool Mos6502DAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) { } R1 = Addr; - R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout())); + R2 = CurDAG->getRegister(M6502::G0, TLI->getPointerTy(CurDAG->getDataLayout())); return true; } @@ -165,18 +165,18 @@ SDNode *Mos6502DAGToDAGISel::Select(SDNode *N) { // Set the Y register to the high-part. SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, + TopPart = SDValue(CurDAG->getMachineNode(M6502::SRAri, dl, MVT::i32, DivLHS, CurDAG->getTargetConstant(31, dl, MVT::i32)), 0); } else { - TopPart = CurDAG->getRegister(SP::G0, MVT::i32); + TopPart = CurDAG->getRegister(M6502::G0, MVT::i32); } - TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart, + TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, M6502::Y, TopPart, SDValue()) .getValue(1); // FIXME: Handle div by immediate. - unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; + unsigned Opcode = N->getOpcode() == ISD::SDIV ? M6502::SDIVrr : M6502::UDIVrr; return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); } @@ -185,7 +185,7 @@ SDNode *Mos6502DAGToDAGISel::Select(SDNode *N) { // FIXME: Handle mul by immediate. SDValue MulLHS = N->getOperand(0); SDValue MulRHS = N->getOperand(1); - unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; + unsigned Opcode = N->getOpcode() == ISD::MULHU ? M6502::UMULrr : M6502::SMULrr; SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MulLHS, MulRHS); SDValue ResultHigh = SDValue(Mul, 1); diff --git a/lib/Target/Mos6502/Mos6502ISelLowering.cpp b/lib/Target/Mos6502/Mos6502ISelLowering.cpp index fe92ea5f6fd..337df3cb3b3 100644 --- a/lib/Target/Mos6502/Mos6502ISelLowering.cpp +++ b/lib/Target/Mos6502/Mos6502ISelLowering.cpp @@ -54,7 +54,7 @@ static bool CC_Mos6502_Assign_f64(unsigned &ValNo, MVT &ValVT, ISD::ArgFlagsTy &ArgFlags, CCState &State) { static const MCPhysReg RegList[] = { - SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 + M6502::I0, M6502::I1, M6502::I2, M6502::I3, M6502::I4, M6502::I5 }; // Try to get first reg. if (unsigned Reg = State.AllocateReg(RegList)) { @@ -93,16 +93,16 @@ static bool CC_Mos650264_Full(unsigned &ValNo, MVT &ValVT, if (LocVT == MVT::i64 && Offset < 6*8) // Promote integers to %i0-%i5. - Reg = SP::I0 + Offset/8; + Reg = M6502::I0 + Offset/8; else if (LocVT == MVT::f64 && Offset < 16*8) // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). - Reg = SP::D0 + Offset/8; + Reg = M6502::D0 + Offset/8; else if (LocVT == MVT::f32 && Offset < 16*8) // Promote floats to %f1, %f3, ... - Reg = SP::F1 + Offset/4; + Reg = M6502::F1 + Offset/4; else if (LocVT == MVT::f128 && Offset < 16*8) // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). - Reg = SP::Q0 + Offset/16; + Reg = M6502::Q0 + Offset/16; // Promote to register when possible, otherwise use the stack slot. if (Reg) { @@ -131,14 +131,14 @@ static bool CC_Mos650264_Half(unsigned &ValNo, MVT &ValVT, if (LocVT == MVT::f32 && Offset < 16*8) { // Promote floats to %f0-%f31. - State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, + State.addLoc(CCValAssign::getReg(ValNo, ValVT, M6502::F0 + Offset/4, LocVT, LocInfo)); return true; } if (LocVT == MVT::i32 && Offset < 6*8) { // Promote integers to %i0-%i5, using half the register. - unsigned Reg = SP::I0 + Offset/8; + unsigned Reg = M6502::I0 + Offset/8; LocVT = MVT::i64; LocInfo = CCValAssign::AExt; @@ -161,9 +161,9 @@ static bool CC_Mos650264_Half(unsigned &ValNo, MVT &ValVT, // callee's register window. This function translates registers to the // corresponding caller window %o register. static unsigned toCallerWindow(unsigned Reg) { - assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); - if (Reg >= SP::I0 && Reg <= SP::I7) - return Reg - SP::I0 + SP::O0; + assert(M6502::I0 + 7 == M6502::I7 && M6502::O0 + 7 == M6502::O7 && "Unexpected enum"); + if (Reg >= M6502::I0 && Reg <= M6502::I7) + return Reg - M6502::I0 + M6502::O0; return Reg; } @@ -223,9 +223,9 @@ Mos6502TargetLowering::LowerReturn_32(SDValue Chain, llvm_unreachable("sret virtual register not created in the entry block"); auto PtrVT = getPointerTy(DAG.getDataLayout()); SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT); - Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); + Chain = DAG.getCopyToReg(Chain, DL, M6502::I0, Val, Flag); Flag = Chain.getValue(1); - RetOps.push_back(DAG.getRegister(SP::I0, PtrVT)); + RetOps.push_back(DAG.getRegister(M6502::I0, PtrVT)); RetAddrOffset = 12; // CallInst + Delay Slot + Unimp } @@ -376,7 +376,7 @@ LowerFormalArguments_32(SDValue Chain, if (VA.isRegLoc()) { if (VA.needsCustom()) { assert(VA.getLocVT() == MVT::f64); - unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + unsigned VRegHi = RegInfo.createVirtualRegister(&M6502::IntRegsRegClass); MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); @@ -393,7 +393,7 @@ LowerFormalArguments_32(SDValue Chain, false, false, false, 0); } else { unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), - &SP::IntRegsRegClass); + &M6502::IntRegsRegClass); LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); } SDValue WholeValue = @@ -402,7 +402,7 @@ LowerFormalArguments_32(SDValue Chain, InVals.push_back(WholeValue); continue; } - unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + unsigned VReg = RegInfo.createVirtualRegister(&M6502::IntRegsRegClass); MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); if (VA.getLocVT() == MVT::f32) @@ -487,7 +487,7 @@ LowerFormalArguments_32(SDValue Chain, Mos6502MachineFunctionInfo *SFI = MF.getInfo(); unsigned Reg = SFI->getSRetReturnReg(); if (!Reg) { - Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); + Reg = MF.getRegInfo().createVirtualRegister(&M6502::IntRegsRegClass); SFI->setSRetReturnReg(Reg); } SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); @@ -497,7 +497,7 @@ LowerFormalArguments_32(SDValue Chain, // Store remaining ArgRegs to the stack if this is a varargs function. if (isVarArg) { static const MCPhysReg ArgRegs[] = { - SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 + M6502::I0, M6502::I1, M6502::I2, M6502::I3, M6502::I4, M6502::I5 }; unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; @@ -515,7 +515,7 @@ LowerFormalArguments_32(SDValue Chain, std::vector OutChains; for (; CurArgReg != ArgRegEnd; ++CurArgReg) { - unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); + unsigned VReg = RegInfo.createVirtualRegister(&M6502::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg, VReg); SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); @@ -636,7 +636,7 @@ LowerFormalArguments_64(SDValue Chain, // of how many arguments were actually passed. SmallVector OutChains; for (; ArgOffset < 6*8; ArgOffset += 8) { - unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); + unsigned VReg = MF.addLiveIn(M6502::I0 + ArgOffset/8, &M6502::I64RegsRegClass); SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); auto PtrVT = getPointerTy(MF.getDataLayout()); @@ -777,7 +777,7 @@ Mos6502TargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, if (Flags.isSRet()) { assert(VA.needsCustom()); // store SRet argument in %sp+64 - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(M6502::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(64, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, @@ -794,7 +794,7 @@ Mos6502TargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, unsigned Offset = VA.getLocMemOffset() + StackOffset; // if it is double-word aligned, just store. if (Offset % 8 == 0) { - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(M6502::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, @@ -827,7 +827,7 @@ Mos6502TargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, } else { // Store the low part in stack. unsigned Offset = NextVA.getLocMemOffset() + StackOffset; - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(M6502::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, @@ -837,7 +837,7 @@ Mos6502TargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, } else { unsigned Offset = VA.getLocMemOffset() + StackOffset; // Store the high part. - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(M6502::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, @@ -868,7 +868,7 @@ Mos6502TargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, assert(VA.isMemLoc()); // Create a store off the stack pointer for this argument. - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(M6502::O6, MVT::i32); SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); @@ -1024,14 +1024,14 @@ static void fixupVariableFloatArgs(SmallVectorImpl &ArgLocs, CCValAssign NewVA; // Determine the offset into the argument array. - unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; + unsigned firstReg = (ValTy == MVT::f64) ? M6502::D0 : M6502::Q0; unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; unsigned Offset = argSize * (VA.getLocReg() - firstReg); assert(Offset < 16*8 && "Offset out of range, bad register enum?"); if (Offset < 6*8) { // This argument should go in %i0-%i5. - unsigned IReg = SP::I0 + Offset/8; + unsigned IReg = M6502::I0 + Offset/8; if (ValTy == MVT::f64) // Full register, just bitconvert into i64. NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), @@ -1131,9 +1131,9 @@ Mos6502TargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, if (VA.needsCustom() && VA.getValVT() == MVT::f128 && VA.getLocVT() == MVT::i128) { // Store and reload into the interger register reg and reg+1. - unsigned Offset = 8 * (VA.getLocReg() - SP::I0); + unsigned Offset = 8 * (VA.getLocReg() - M6502::I0); unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; - SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); + SDValue StackPtr = DAG.getRegister(M6502::O6, PtrVT); SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL); HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff); SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL); @@ -1181,7 +1181,7 @@ Mos6502TargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, assert(VA.isMemLoc()); // Create a store off the stack pointer for this argument. - SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); + SDValue StackPtr = DAG.getRegister(M6502::O6, PtrVT); // The argument area starts at %fp+BIAS+128 in the callee frame, // %sp+BIAS+128 in ours. SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + @@ -1373,12 +1373,12 @@ Mos6502TargetLowering::Mos6502TargetLowering(TargetMachine &TM, MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); // Set up the register classes. - addRegisterClass(MVT::i32, &SP::IntRegsRegClass); - addRegisterClass(MVT::f32, &SP::FPRegsRegClass); - addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); - addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); + addRegisterClass(MVT::i32, &M6502::IntRegsRegClass); + addRegisterClass(MVT::f32, &M6502::FPRegsRegClass); + addRegisterClass(MVT::f64, &M6502::DFPRegsRegClass); + addRegisterClass(MVT::f128, &M6502::QFPRegsRegClass); if (Subtarget->is64Bit()) - addRegisterClass(MVT::i64, &SP::I64RegsRegClass); + addRegisterClass(MVT::i64, &M6502::I64RegsRegClass); // Turn FP extload into load/fextend for (MVT VT : MVT::fp_valuetypes()) { @@ -1579,10 +1579,10 @@ Mos6502TargetLowering::Mos6502TargetLowering(TargetMachine &TM, setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - setExceptionPointerRegister(SP::I0); - setExceptionSelectorRegister(SP::I1); + setExceptionPointerRegister(M6502::I0); + setExceptionSelectorRegister(M6502::I1); - setStackPointerRegisterToSaveRestore(SP::O6); + setStackPointerRegisterToSaveRestore(M6502::O6); setOperationAction(ISD::CTPOP, MVT::i32, Subtarget->usePopc() ? Legal : Expand); @@ -1904,7 +1904,7 @@ SDValue Mos6502TargetLowering::LowerGlobalTLSAddress(SDValue Op, SDValue InFlag; Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL); - Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); + Chain = DAG.getCopyToReg(Chain, DL, M6502::O0, Argument, InFlag); InFlag = Chain.getValue(1); SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); SDValue Symbol = withTargetFlags(Op, callTF, DAG); @@ -1914,7 +1914,7 @@ SDValue Mos6502TargetLowering::LowerGlobalTLSAddress(SDValue Op, Ops.push_back(Chain); Ops.push_back(Callee); Ops.push_back(Symbol); - Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); + Ops.push_back(DAG.getRegister(M6502::O0, PtrVT)); const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask( DAG.getMachineFunction(), CallingConv::C); assert(Mask && "Missing call preserved mask for calling convention"); @@ -1925,7 +1925,7 @@ SDValue Mos6502TargetLowering::LowerGlobalTLSAddress(SDValue Op, Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true), DAG.getIntPtrConstant(0, DL, true), InFlag, DL); InFlag = Chain.getValue(1); - SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); + SDValue Ret = DAG.getCopyFromReg(Chain, DL, M6502::O0, PtrVT, InFlag); if (model != TLSModel::LocalDynamic) return Ret; @@ -1958,7 +1958,7 @@ SDValue Mos6502TargetLowering::LowerGlobalTLSAddress(SDValue Op, DL, PtrVT, Ptr, withTargetFlags(Op, ldTF, DAG)); return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, - DAG.getRegister(SP::G7, PtrVT), Offset, + DAG.getRegister(M6502::G7, PtrVT), Offset, withTargetFlags(Op, Mos6502MCExpr::VK_Mos6502_TLS_IE_ADD, DAG)); } @@ -1971,7 +1971,7 @@ SDValue Mos6502TargetLowering::LowerGlobalTLSAddress(SDValue Op, SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); return DAG.getNode(ISD::ADD, DL, PtrVT, - DAG.getRegister(SP::G7, PtrVT), Offset); + DAG.getRegister(M6502::G7, PtrVT), Offset); } SDValue @@ -2379,7 +2379,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, // memory location argument. SDLoc DL(Op); SDValue Offset = - DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), + DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(M6502::I6, PtrVT), DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL)); const Value *SV = cast(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), @@ -2417,7 +2417,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, EVT VT = Size->getValueType(0); SDLoc dl(Op); - unsigned SPReg = SP::O6; + unsigned SPReg = M6502::O6; SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain @@ -2448,7 +2448,7 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, EVT VT = Op.getValueType(); SDLoc dl(Op); - unsigned FrameReg = SP::I6; + unsigned FrameReg = M6502::I6; unsigned stackBias = Subtarget->getStackPointerBias(); SDValue FrameAddr; @@ -2506,7 +2506,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, SDValue RetAddr; if (depth == 0) { auto PtrVT = TLI.getPointerTy(DAG.getDataLayout()); - unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); + unsigned RetReg = MF.addLiveIn(M6502::I7, TLI.getRegClassFor(PtrVT)); RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); return RetAddr; } @@ -2537,18 +2537,18 @@ static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd. SDValue SrcReg64 = Op.getOperand(0); - SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, + SDValue Hi32 = DAG.getTargetExtractSubreg(M6502::sub_even, dl, MVT::f32, SrcReg64); - SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, + SDValue Lo32 = DAG.getTargetExtractSubreg(M6502::sub_odd, dl, MVT::f32, SrcReg64); Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0); - DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, + DstReg64 = DAG.getTargetInsertSubreg(M6502::sub_even, dl, MVT::f64, DstReg64, Hi32); - DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, + DstReg64 = DAG.getTargetInsertSubreg(M6502::sub_odd, dl, MVT::f64, DstReg64, Lo32); return DstReg64; } @@ -2582,8 +2582,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) LdNode->getPointerInfo(), false, false, false, alignment); - SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); - SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); + SDValue SubRegEven = DAG.getTargetConstant(M6502::sub_even64, dl, MVT::i32); + SDValue SubRegOdd = DAG.getTargetConstant(M6502::sub_odd64, dl, MVT::i32); SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f128); @@ -2610,8 +2610,8 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { StoreSDNode *StNode = dyn_cast(Op.getNode()); assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF && "Unexpected node type"); - SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); - SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); + SDValue SubRegEven = DAG.getTargetConstant(M6502::sub_even64, dl, MVT::i32); + SDValue SubRegOdd = DAG.getTargetConstant(M6502::sub_odd64, dl, MVT::i32); SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, @@ -2662,9 +2662,9 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { SDLoc dl(Op); SDValue SrcReg128 = Op.getOperand(0); - SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, + SDValue Hi64 = DAG.getTargetExtractSubreg(M6502::sub_even64, dl, MVT::f64, SrcReg128); - SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, + SDValue Lo64 = DAG.getTargetExtractSubreg(M6502::sub_odd64, dl, MVT::f64, SrcReg128); if (isV9) Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); @@ -2673,9 +2673,9 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f128), 0); - DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, + DstReg128 = DAG.getTargetInsertSubreg(M6502::sub_even64, dl, MVT::f128, DstReg128, Hi64); - DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, + DstReg128 = DAG.getTargetInsertSubreg(M6502::sub_odd64, dl, MVT::f128, DstReg128, Lo64); return DstReg128; } @@ -2853,61 +2853,61 @@ Mos6502TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { switch (MI->getOpcode()) { default: llvm_unreachable("Unknown SELECT_CC!"); - case SP::SELECT_CC_Int_ICC: - case SP::SELECT_CC_FP_ICC: - case SP::SELECT_CC_DFP_ICC: - case SP::SELECT_CC_QFP_ICC: - return expandSelectCC(MI, BB, SP::BCOND); - case SP::SELECT_CC_Int_FCC: - case SP::SELECT_CC_FP_FCC: - case SP::SELECT_CC_DFP_FCC: - case SP::SELECT_CC_QFP_FCC: - return expandSelectCC(MI, BB, SP::FBCOND); + case M6502::SELECT_CC_Int_ICC: + case M6502::SELECT_CC_FP_ICC: + case M6502::SELECT_CC_DFP_ICC: + case M6502::SELECT_CC_QFP_ICC: + return expandSelectCC(MI, BB, M6502::BCOND); + case M6502::SELECT_CC_Int_FCC: + case M6502::SELECT_CC_FP_FCC: + case M6502::SELECT_CC_DFP_FCC: + case M6502::SELECT_CC_QFP_FCC: + return expandSelectCC(MI, BB, M6502::FBCOND); - case SP::ATOMIC_LOAD_ADD_32: - return expandAtomicRMW(MI, BB, SP::ADDrr); - case SP::ATOMIC_LOAD_ADD_64: - return expandAtomicRMW(MI, BB, SP::ADDXrr); - case SP::ATOMIC_LOAD_SUB_32: - return expandAtomicRMW(MI, BB, SP::SUBrr); - case SP::ATOMIC_LOAD_SUB_64: - return expandAtomicRMW(MI, BB, SP::SUBXrr); - case SP::ATOMIC_LOAD_AND_32: - return expandAtomicRMW(MI, BB, SP::ANDrr); - case SP::ATOMIC_LOAD_AND_64: - return expandAtomicRMW(MI, BB, SP::ANDXrr); - case SP::ATOMIC_LOAD_OR_32: - return expandAtomicRMW(MI, BB, SP::ORrr); - case SP::ATOMIC_LOAD_OR_64: - return expandAtomicRMW(MI, BB, SP::ORXrr); - case SP::ATOMIC_LOAD_XOR_32: - return expandAtomicRMW(MI, BB, SP::XORrr); - case SP::ATOMIC_LOAD_XOR_64: - return expandAtomicRMW(MI, BB, SP::XORXrr); - case SP::ATOMIC_LOAD_NAND_32: - return expandAtomicRMW(MI, BB, SP::ANDrr); - case SP::ATOMIC_LOAD_NAND_64: - return expandAtomicRMW(MI, BB, SP::ANDXrr); + case M6502::ATOMIC_LOAD_ADD_32: + return expandAtomicRMW(MI, BB, M6502::ADDrr); + case M6502::ATOMIC_LOAD_ADD_64: + return expandAtomicRMW(MI, BB, M6502::ADDXrr); + case M6502::ATOMIC_LOAD_SUB_32: + return expandAtomicRMW(MI, BB, M6502::SUBrr); + case M6502::ATOMIC_LOAD_SUB_64: + return expandAtomicRMW(MI, BB, M6502::SUBXrr); + case M6502::ATOMIC_LOAD_AND_32: + return expandAtomicRMW(MI, BB, M6502::ANDrr); + case M6502::ATOMIC_LOAD_AND_64: + return expandAtomicRMW(MI, BB, M6502::ANDXrr); + case M6502::ATOMIC_LOAD_OR_32: + return expandAtomicRMW(MI, BB, M6502::ORrr); + case M6502::ATOMIC_LOAD_OR_64: + return expandAtomicRMW(MI, BB, M6502::ORXrr); + case M6502::ATOMIC_LOAD_XOR_32: + return expandAtomicRMW(MI, BB, M6502::XORrr); + case M6502::ATOMIC_LOAD_XOR_64: + return expandAtomicRMW(MI, BB, M6502::XORXrr); + case M6502::ATOMIC_LOAD_NAND_32: + return expandAtomicRMW(MI, BB, M6502::ANDrr); + case M6502::ATOMIC_LOAD_NAND_64: + return expandAtomicRMW(MI, BB, M6502::ANDXrr); - case SP::ATOMIC_SWAP_64: + case M6502::ATOMIC_SWAP_64: return expandAtomicRMW(MI, BB, 0); - case SP::ATOMIC_LOAD_MAX_32: - return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G); - case SP::ATOMIC_LOAD_MAX_64: - return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G); - case SP::ATOMIC_LOAD_MIN_32: - return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE); - case SP::ATOMIC_LOAD_MIN_64: - return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE); - case SP::ATOMIC_LOAD_UMAX_32: - return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU); - case SP::ATOMIC_LOAD_UMAX_64: - return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU); - case SP::ATOMIC_LOAD_UMIN_32: - return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU); - case SP::ATOMIC_LOAD_UMIN_64: - return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU); + case M6502::ATOMIC_LOAD_MAX_32: + return expandAtomicRMW(MI, BB, M6502::MOVICCrr, SPCC::ICC_G); + case M6502::ATOMIC_LOAD_MAX_64: + return expandAtomicRMW(MI, BB, M6502::MOVXCCrr, SPCC::ICC_G); + case M6502::ATOMIC_LOAD_MIN_32: + return expandAtomicRMW(MI, BB, M6502::MOVICCrr, SPCC::ICC_LE); + case M6502::ATOMIC_LOAD_MIN_64: + return expandAtomicRMW(MI, BB, M6502::MOVXCCrr, SPCC::ICC_LE); + case M6502::ATOMIC_LOAD_UMAX_32: + return expandAtomicRMW(MI, BB, M6502::MOVICCrr, SPCC::ICC_GU); + case M6502::ATOMIC_LOAD_UMAX_64: + return expandAtomicRMW(MI, BB, M6502::MOVXCCrr, SPCC::ICC_GU); + case M6502::ATOMIC_LOAD_UMIN_32: + return expandAtomicRMW(MI, BB, M6502::MOVICCrr, SPCC::ICC_LEU); + case M6502::ATOMIC_LOAD_UMIN_64: + return expandAtomicRMW(MI, BB, M6502::MOVXCCrr, SPCC::ICC_LEU); } } @@ -2963,7 +2963,7 @@ Mos6502TargetLowering::expandSelectCC(MachineInstr *MI, // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) + BuildMI(*BB, BB->begin(), dl, TII.get(M6502::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); @@ -3001,12 +3001,12 @@ Mos6502TargetLowering::expandAtomicRMW(MachineInstr *MI, // bne loop // done: // - bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); + bool is64Bit = M6502::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); const TargetRegisterClass *ValueRC = - is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; + is64Bit ? &M6502::I64RegsRegClass : &M6502::IntRegsRegClass; unsigned Val0Reg = MRI.createVirtualRegister(ValueRC); - BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) + BuildMI(*MBB, MI, DL, TII.get(is64Bit ? M6502::LDXri : M6502::LDri), Val0Reg) .addReg(AddrReg).addImm(0); // Split the basic block MBB before MI and insert the loop block in the hole. @@ -3033,14 +3033,14 @@ Mos6502TargetLowering::expandAtomicRMW(MachineInstr *MI, // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP). unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg); - BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg) + BuildMI(LoopMBB, DL, TII.get(M6502::PHI), ValReg) .addReg(Val0Reg).addMBB(MBB) .addReg(DestReg).addMBB(LoopMBB); if (CondCode) { // This is one of the min/max operations. We need a CMPrr followed by a // MOVXCC/MOVICC. - BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg); + BuildMI(LoopMBB, DL, TII.get(M6502::CMPrr)).addReg(ValReg).addReg(Rs2Reg); BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode); } else if (Opcode) { @@ -3048,18 +3048,18 @@ Mos6502TargetLowering::expandAtomicRMW(MachineInstr *MI, .addReg(ValReg).addReg(Rs2Reg); } - if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 || - MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) { + if (MI->getOpcode() == M6502::ATOMIC_LOAD_NAND_32 || + MI->getOpcode() == M6502::ATOMIC_LOAD_NAND_64) { unsigned TmpReg = UpdReg; UpdReg = MRI.createVirtualRegister(ValueRC); - BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); + BuildMI(LoopMBB, DL, TII.get(M6502::XORri), UpdReg).addReg(TmpReg).addImm(-1); } - BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) + BuildMI(LoopMBB, DL, TII.get(is64Bit ? M6502::CASXrr : M6502::CASrr), DestReg) .addReg(AddrReg).addReg(ValReg).addReg(UpdReg) .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); - BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); - BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) + BuildMI(LoopMBB, DL, TII.get(M6502::CMPrr)).addReg(ValReg).addReg(DestReg); + BuildMI(LoopMBB, DL, TII.get(is64Bit ? M6502::BPXCC : M6502::BCOND)) .addMBB(LoopMBB).addImm(SPCC::ICC_NE); MI->eraseFromParent(); @@ -3152,7 +3152,7 @@ Mos6502TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TR if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': - return std::make_pair(0U, &SP::IntRegsRegClass); + return std::make_pair(0U, &M6502::IntRegsRegClass); } } else if (!Constraint.empty() && Constraint.size() <= 5 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') { diff --git a/lib/Target/Mos6502/Mos6502InstrFormats.td b/lib/Target/Mos6502/Mos6502InstrFormats.td index 078cadc71a8..7a6dc03dbf5 100644 --- a/lib/Target/Mos6502/Mos6502InstrFormats.td +++ b/lib/Target/Mos6502/Mos6502InstrFormats.td @@ -11,7 +11,7 @@ class InstSP pattern> : Instruction { field bits<32> Inst; - let Namespace = "SP"; + let Namespace = "M6502"; let Size = 4; bits<2> op; diff --git a/lib/Target/Mos6502/Mos6502InstrInfo.cpp b/lib/Target/Mos6502/Mos6502InstrInfo.cpp index b8ad6954d04..0d1cc05ced4 100644 --- a/lib/Target/Mos6502/Mos6502InstrInfo.cpp +++ b/lib/Target/Mos6502/Mos6502InstrInfo.cpp @@ -33,7 +33,7 @@ using namespace llvm; void Mos6502InstrInfo::anchor() {} Mos6502InstrInfo::Mos6502InstrInfo(Mos6502Subtarget &ST) - : Mos6502GenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), + : Mos6502GenInstrInfo(M6502::ADJCALLSTACKDOWN, M6502::ADJCALLSTACKUP), RI(), Subtarget(ST) {} /// isLoadFromStackSlot - If the specified machine instruction is a direct @@ -43,11 +43,11 @@ Mos6502InstrInfo::Mos6502InstrInfo(Mos6502Subtarget &ST) /// any side effects other than loading from the stack slot. unsigned Mos6502InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { - if (MI->getOpcode() == SP::LDri || - MI->getOpcode() == SP::LDXri || - MI->getOpcode() == SP::LDFri || - MI->getOpcode() == SP::LDDFri || - MI->getOpcode() == SP::LDQFri) { + if (MI->getOpcode() == M6502::LDri || + MI->getOpcode() == M6502::LDXri || + MI->getOpcode() == M6502::LDFri || + MI->getOpcode() == M6502::LDDFri || + MI->getOpcode() == M6502::LDQFri) { if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { FrameIndex = MI->getOperand(1).getIndex(); @@ -64,11 +64,11 @@ unsigned Mos6502InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, /// any side effects other than storing to the stack slot. unsigned Mos6502InstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { - if (MI->getOpcode() == SP::STri || - MI->getOpcode() == SP::STXri || - MI->getOpcode() == SP::STFri || - MI->getOpcode() == SP::STDFri || - MI->getOpcode() == SP::STQFri) { + if (MI->getOpcode() == M6502::STri || + MI->getOpcode() == M6502::STXri || + MI->getOpcode() == M6502::STFri || + MI->getOpcode() == M6502::STDFri || + MI->getOpcode() == M6502::STQFri) { if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) { FrameIndex = MI->getOperand(0).getIndex(); @@ -148,7 +148,7 @@ bool Mos6502InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, return true; // Handle Unconditional branches. - if (I->getOpcode() == SP::BA) { + if (I->getOpcode() == M6502::BA) { UnCondBrIter = I; if (!AllowModify) { @@ -175,7 +175,7 @@ bool Mos6502InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, } unsigned Opcode = I->getOpcode(); - if (Opcode != SP::BCOND && Opcode != SP::FBCOND) + if (Opcode != M6502::BCOND && Opcode != M6502::FBCOND) return true; // Unknown Opcode. SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); @@ -204,7 +204,7 @@ bool Mos6502InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator OldInst = I; BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); - BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) + BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(M6502::BA)) .addMBB(TargetBB); OldInst->eraseFromParent(); @@ -237,7 +237,7 @@ Mos6502InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, if (Cond.empty()) { assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); + BuildMI(&MBB, DL, get(M6502::BA)).addMBB(TBB); return 1; } @@ -245,13 +245,13 @@ Mos6502InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, unsigned CC = Cond[0].getImm(); if (IsIntegerCC(CC)) - BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); + BuildMI(&MBB, DL, get(M6502::BCOND)).addMBB(TBB).addImm(CC); else - BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); + BuildMI(&MBB, DL, get(M6502::FBCOND)).addMBB(TBB).addImm(CC); if (!FBB) return 1; - BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); + BuildMI(&MBB, DL, get(M6502::BA)).addMBB(FBB); return 2; } @@ -265,9 +265,9 @@ unsigned Mos6502InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const if (I->isDebugValue()) continue; - if (I->getOpcode() != SP::BA - && I->getOpcode() != SP::BCOND - && I->getOpcode() != SP::FBCOND) + if (I->getOpcode() != M6502::BA + && I->getOpcode() != M6502::BCOND + && I->getOpcode() != M6502::FBCOND) break; // Not a branch I->eraseFromParent(); @@ -285,53 +285,53 @@ void Mos6502InstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned movOpc = 0; const unsigned *subRegIdx = nullptr; - const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; - const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; - const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, - SP::sub_odd64_then_sub_even, - SP::sub_odd64_then_sub_odd }; + const unsigned DFP_FP_SubRegsIdx[] = { M6502::sub_even, M6502::sub_odd }; + const unsigned QFP_DFP_SubRegsIdx[] = { M6502::sub_even64, M6502::sub_odd64 }; + const unsigned QFP_FP_SubRegsIdx[] = { M6502::sub_even, M6502::sub_odd, + M6502::sub_odd64_then_sub_even, + M6502::sub_odd64_then_sub_odd }; - if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) - BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) + if (M6502::IntRegsRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, I, DL, get(M6502::ORrr), DestReg).addReg(M6502::G0) .addReg(SrcReg, getKillRegState(KillSrc)); - else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) - BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) + else if (M6502::FPRegsRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, I, DL, get(M6502::FMOVS), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); - else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { + else if (M6502::DFPRegsRegClass.contains(DestReg, SrcReg)) { if (Subtarget.isV9()) { - BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) + BuildMI(MBB, I, DL, get(M6502::FMOVD), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); } else { // Use two FMOVS instructions. subRegIdx = DFP_FP_SubRegsIdx; numSubRegs = 2; - movOpc = SP::FMOVS; + movOpc = M6502::FMOVS; } - } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { + } else if (M6502::QFPRegsRegClass.contains(DestReg, SrcReg)) { if (Subtarget.isV9()) { if (Subtarget.hasHardQuad()) { - BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) + BuildMI(MBB, I, DL, get(M6502::FMOVQ), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); } else { // Use two FMOVD instructions. subRegIdx = QFP_DFP_SubRegsIdx; numSubRegs = 2; - movOpc = SP::FMOVD; + movOpc = M6502::FMOVD; } } else { // Use four FMOVS instructions. subRegIdx = QFP_FP_SubRegsIdx; numSubRegs = 4; - movOpc = SP::FMOVS; + movOpc = M6502::FMOVS; } - } else if (SP::ASRRegsRegClass.contains(DestReg) && - SP::IntRegsRegClass.contains(SrcReg)) { - BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) - .addReg(SP::G0) + } else if (M6502::ASRRegsRegClass.contains(DestReg) && + M6502::IntRegsRegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(M6502::WRASRrr), DestReg) + .addReg(M6502::G0) .addReg(SrcReg, getKillRegState(KillSrc)); - } else if (SP::IntRegsRegClass.contains(DestReg) && - SP::ASRRegsRegClass.contains(SrcReg)) { - BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) + } else if (M6502::IntRegsRegClass.contains(DestReg) && + M6502::ASRRegsRegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(M6502::RDASR), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); } else llvm_unreachable("Impossible reg-to-reg copy"); @@ -372,22 +372,22 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MFI.getObjectAlignment(FI)); // On the order of operands here: think "[FrameIdx + 0] = SrcReg". - if (RC == &SP::I64RegsRegClass) - BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) + if (RC == &M6502::I64RegsRegClass) + BuildMI(MBB, I, DL, get(M6502::STXri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - else if (RC == &SP::IntRegsRegClass) - BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) + else if (RC == &M6502::IntRegsRegClass) + BuildMI(MBB, I, DL, get(M6502::STri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - else if (RC == &SP::FPRegsRegClass) - BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) + else if (RC == &M6502::FPRegsRegClass) + BuildMI(MBB, I, DL, get(M6502::STFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) - BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) + else if (M6502::DFPRegsRegClass.hasSubClassEq(RC)) + BuildMI(MBB, I, DL, get(M6502::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) + else if (M6502::QFPRegsRegClass.hasSubClassEq(RC)) // Use STQFri irrespective of its legality. If STQ is not legal, it will be // lowered into two STDs in eliminateFrameIndex. - BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(M6502::STQFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); else llvm_unreachable("Can't store this register to stack slot"); @@ -409,22 +409,22 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); - if (RC == &SP::I64RegsRegClass) - BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) + if (RC == &M6502::I64RegsRegClass) + BuildMI(MBB, I, DL, get(M6502::LDXri), DestReg).addFrameIndex(FI).addImm(0) .addMemOperand(MMO); - else if (RC == &SP::IntRegsRegClass) - BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) + else if (RC == &M6502::IntRegsRegClass) + BuildMI(MBB, I, DL, get(M6502::LDri), DestReg).addFrameIndex(FI).addImm(0) .addMemOperand(MMO); - else if (RC == &SP::FPRegsRegClass) - BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) + else if (RC == &M6502::FPRegsRegClass) + BuildMI(MBB, I, DL, get(M6502::LDFri), DestReg).addFrameIndex(FI).addImm(0) .addMemOperand(MMO); - else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) - BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) + else if (M6502::DFPRegsRegClass.hasSubClassEq(RC)) + BuildMI(MBB, I, DL, get(M6502::LDDFri), DestReg).addFrameIndex(FI).addImm(0) .addMemOperand(MMO); - else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) + else if (M6502::QFPRegsRegClass.hasSubClassEq(RC)) // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be // lowered into two LDDs in eliminateFrameIndex. - BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) + BuildMI(MBB, I, DL, get(M6502::LDQFri), DestReg).addFrameIndex(FI).addImm(0) .addMemOperand(MMO); else llvm_unreachable("Can't load this register from stack slot"); @@ -443,12 +443,12 @@ unsigned Mos6502InstrInfo::getGlobalBaseReg(MachineFunction *MF) const MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *PtrRC = - Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; + Subtarget.is64Bit() ? &M6502::I64RegsRegClass : &M6502::IntRegsRegClass; GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC); DebugLoc dl; - BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); + BuildMI(FirstMBB, MBBI, dl, get(M6502::GETPCX), GlobalBaseReg); Mos6502FI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } diff --git a/lib/Target/Mos6502/Mos6502RegisterInfo.cpp b/lib/Target/Mos6502/Mos6502RegisterInfo.cpp index bf9b86a2ab7..927e2e6d82d 100644 --- a/lib/Target/Mos6502/Mos6502RegisterInfo.cpp +++ b/lib/Target/Mos6502/Mos6502RegisterInfo.cpp @@ -34,7 +34,7 @@ static cl::opt ReserveAppRegisters("mos6502-reserve-app-registers", cl::Hidden, cl::init(false), cl::desc("Reserve application registers (%g2-%g4)")); -Mos6502RegisterInfo::Mos6502RegisterInfo() : Mos6502GenRegisterInfo(SP::O7) {} +Mos6502RegisterInfo::Mos6502RegisterInfo() : Mos6502GenRegisterInfo(M6502::O7) {} const MCPhysReg* Mos6502RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { @@ -56,29 +56,29 @@ BitVector Mos6502RegisterInfo::getReservedRegs(const MachineFunction &MF) const BitVector Reserved(getNumRegs()); const Mos6502Subtarget &Subtarget = MF.getSubtarget(); // FIXME: G1 reserved for now for large imm generation by frame code. - Reserved.set(SP::G1); + Reserved.set(M6502::G1); // G1-G4 can be used in applications. if (ReserveAppRegisters) { - Reserved.set(SP::G2); - Reserved.set(SP::G3); - Reserved.set(SP::G4); + Reserved.set(M6502::G2); + Reserved.set(M6502::G3); + Reserved.set(M6502::G4); } // G5 is not reserved in 64 bit mode. if (!Subtarget.is64Bit()) - Reserved.set(SP::G5); + Reserved.set(M6502::G5); - Reserved.set(SP::O6); - Reserved.set(SP::I6); - Reserved.set(SP::I7); - Reserved.set(SP::G0); - Reserved.set(SP::G6); - Reserved.set(SP::G7); + Reserved.set(M6502::O6); + Reserved.set(M6502::I6); + Reserved.set(M6502::I7); + Reserved.set(M6502::G0); + Reserved.set(M6502::G6); + Reserved.set(M6502::G7); // Unaliased double registers are not available in non-V9 targets. if (!Subtarget.isV9()) { for (unsigned n = 0; n != 16; ++n) { - for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) + for (MCRegAliasIterator AI(M6502::D16 + n, this, true); AI.isValid(); ++AI) Reserved.set(*AI); } } @@ -90,7 +90,7 @@ const TargetRegisterClass* Mos6502RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const { const Mos6502Subtarget &Subtarget = MF.getSubtarget(); - return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; + return Subtarget.is64Bit() ? &M6502::I64RegsRegClass : &M6502::IntRegsRegClass; } static void replaceFI(MachineFunction &MF, @@ -118,15 +118,15 @@ static void replaceFI(MachineFunction &MF, // sethi %hi(Offset), %g1 // add %g1, %fp, %g1 // Insert G1+%lo(offset) into the user. - BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::SETHIi), M6502::G1) .addImm(HI22(Offset)); // Emit G1 = G1 + I6 - BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::ADDrr), M6502::G1).addReg(M6502::G1) .addReg(FramePtr); // Insert: G1+%lo(offset) into the user. - MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); + MI.getOperand(FIOperandNum).ChangeToRegister(M6502::G1, false); MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset)); return; } @@ -136,15 +136,15 @@ static void replaceFI(MachineFunction &MF, // xor %g1, %lox(offset), %g1 // add %g1, %fp, %g1 // Insert: G1 + 0 into the user. - BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::SETHIi), M6502::G1) .addImm(HIX22(Offset)); - BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) - .addReg(SP::G1).addImm(LOX10(Offset)); + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::XORri), M6502::G1) + .addReg(M6502::G1).addImm(LOX10(Offset)); - BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::ADDrr), M6502::G1).addReg(M6502::G1) .addReg(FramePtr); // Insert: G1+%lo(offset) into the user. - MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); + MI.getOperand(FIOperandNum).ChangeToRegister(M6502::G1, false); MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); } @@ -166,38 +166,38 @@ Mos6502RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(FIOperandNum + 1).getImm() + Subtarget.getStackPointerBias(); Mos6502MachineFunctionInfo *FuncInfo = MF.getInfo(); - unsigned FramePtr = SP::I6; + unsigned FramePtr = M6502::I6; if (FuncInfo->isLeafProc()) { // Use %sp and adjust offset if needed. - FramePtr = SP::O6; + FramePtr = M6502::O6; int stackSize = MF.getFrameInfo()->getStackSize(); Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ; } if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { - if (MI.getOpcode() == SP::STQFri) { + if (MI.getOpcode() == M6502::STQFri) { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); unsigned SrcReg = MI.getOperand(2).getReg(); - unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); - unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); + unsigned SrcEvenReg = getSubReg(SrcReg, M6502::sub_even64); + unsigned SrcOddReg = getSubReg(SrcReg, M6502::sub_odd64); MachineInstr *StMI = - BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::STDFri)) .addReg(FramePtr).addImm(0).addReg(SrcEvenReg); replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr); - MI.setDesc(TII.get(SP::STDFri)); + MI.setDesc(TII.get(M6502::STDFri)); MI.getOperand(2).setReg(SrcOddReg); Offset += 8; - } else if (MI.getOpcode() == SP::LDQFri) { + } else if (MI.getOpcode() == M6502::LDQFri) { const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); unsigned DestReg = MI.getOperand(0).getReg(); - unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); - unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); + unsigned DestEvenReg = getSubReg(DestReg, M6502::sub_even64); + unsigned DestOddReg = getSubReg(DestReg, M6502::sub_odd64); MachineInstr *StMI = - BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg) + BuildMI(*MI.getParent(), II, dl, TII.get(M6502::LDDFri), DestEvenReg) .addReg(FramePtr).addImm(0); replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr); - MI.setDesc(TII.get(SP::LDDFri)); + MI.setDesc(TII.get(M6502::LDDFri)); MI.getOperand(0).setReg(DestOddReg); Offset += 8; } @@ -208,6 +208,6 @@ Mos6502RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned Mos6502RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - return SP::I6; + return M6502::I6; } diff --git a/lib/Target/Mos6502/Mos6502RegisterInfo.td b/lib/Target/Mos6502/Mos6502RegisterInfo.td index 4eb94911d36..b76a9e3af0c 100644 --- a/lib/Target/Mos6502/Mos6502RegisterInfo.td +++ b/lib/Target/Mos6502/Mos6502RegisterInfo.td @@ -13,15 +13,15 @@ class Mos6502Reg Enc, string n> : Register { let HWEncoding = Enc; - let Namespace = "SP"; + let Namespace = "M6502"; } class Mos6502CtrlReg Enc, string n>: Register { let HWEncoding = Enc; - let Namespace = "SP"; + let Namespace = "M6502"; } -let Namespace = "SP" in { +let Namespace = "M6502" in { def sub_even : SubRegIndex<32>; def sub_odd : SubRegIndex<32, 32>; def sub_even64 : SubRegIndex<64>; @@ -225,7 +225,7 @@ def Q15 : Rq<29, "F60", [D30, D31]>; // This register class should not be used to hold i64 values, use the I64Regs // register class for that. The i64 type is included here to allow i64 patterns // using the integer instructions. -def IntRegs : RegisterClass<"SP", [i32, i64], 32, +def IntRegs : RegisterClass<"M6502", [i32, i64], 32, (add (sequence "I%u", 0, 7), (sequence "G%u", 0, 7), (sequence "L%u", 0, 7), @@ -235,20 +235,20 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32, // These are the same as the 32-bit registers, so TableGen will consider this // to be a sub-class of IntRegs. That works out because requiring a 64-bit // spill slot is a stricter constraint than only requiring a 32-bit spill slot. -def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; +def I64Regs : RegisterClass<"M6502", [i64], 64, (add IntRegs)>; // Floating point register classes. -def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; +def FPRegs : RegisterClass<"M6502", [f32], 32, (sequence "F%u", 0, 31)>; -def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; +def DFPRegs : RegisterClass<"M6502", [f64], 64, (sequence "D%u", 0, 31)>; -def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; +def QFPRegs : RegisterClass<"M6502", [f128], 128, (sequence "Q%u", 0, 15)>; // Floating point control register classes. -def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; +def FCCRegs : RegisterClass<"M6502", [i1], 1, (sequence "FCC%u", 0, 3)>; // Ancillary state registers -def ASRRegs : RegisterClass<"SP", [i32], 32, +def ASRRegs : RegisterClass<"M6502", [i32], 32, (add Y, (sequence "ASR%u", 1, 31))> { let isAllocatable = 0; }