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Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-20 06:59:32 +00:00
parent 401e10c4fb
commit f6fe957950
2 changed files with 15 additions and 3 deletions
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4
lib/Target/ARM/README-Thumb.txt
View File

@ -244,3 +244,7 @@ to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
//===---------------------------------------------------------------------===//
Thumb1 immediate field sometimes keep pre-scaled values. See
Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
Thumb2.

14
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -231,8 +231,16 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (DestReg != BaseReg)
DstNotEqBase = true;
NumBits = 8;
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
NeedPred = NeedCC = true;
if (DestReg == ARM::SP) {
Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
NumBits = 7;
Scale = 4;
} else {
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
NumBits = 8;
NeedPred = NeedCC = true;
}
isTwoAddr = true;
}
@ -447,7 +455,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
removeOperands(MI, i);
MachineInstrBuilder MIB(&MI);
AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
.addImm(Offset/Scale));
.addImm(Offset / Scale));
} else {
MI.getOperand(i).ChangeToRegister(FrameReg, false);
MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);