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https://github.com/c64scene-ar/llvm-6502.git
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Initial x86 support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -329,6 +329,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO));
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = LowerSymbolOperand(MO, AsmPrinter.GetBlockAddressSymbol(
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MO.getBlockAddress()));
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break;
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}
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OutMI.addOperand(MCOp);
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@ -328,11 +328,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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if (Subtarget->is64Bit())
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
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setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
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setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
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setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
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setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
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}
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// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
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setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
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@ -4692,6 +4694,24 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
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return Result;
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}
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SDValue
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X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
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unsigned WrapperKind = X86ISD::Wrapper;
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CodeModel::Model M = getTargetMachine().getCodeModel();
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if (Subtarget->isPICStyleRIPRel() &&
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(M == CodeModel::Small || M == CodeModel::Kernel))
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WrapperKind = X86ISD::WrapperRIP;
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DebugLoc DL = Op.getDebugLoc();
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BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
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SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true);
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Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
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return Result;
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}
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SDValue
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X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
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int64_t Offset,
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@ -7019,6 +7039,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
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case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
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case ISD::SHL_PARTS:
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case ISD::SRA_PARTS:
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case ISD::SRL_PARTS: return LowerShift(Op, DAG);
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@ -635,6 +635,7 @@ namespace llvm {
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SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
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int64_t Offset, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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@ -1595,6 +1595,8 @@ def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
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// In static codegen with small code model, we can get the address of a label
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// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
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@ -1607,6 +1609,8 @@ def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
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// In kernel code model, we can get the address of a label
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// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
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@ -1619,6 +1623,8 @@ def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
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// If we have small model and -static mode, it is safe to store global addresses
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// directly as immediates. FIXME: This is really a hack, the 'imm' predicate
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@ -1635,6 +1641,9 @@ def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, texternalsym:$src)>,
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Requires<[NearData, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tblockaddress:$src)>,
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Requires<[NearData, IsStatic]>;
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// Calls
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// Direct PC relative function call for small code model. 32-bit displacement
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@ -3789,6 +3789,7 @@ def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
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def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
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def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
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def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
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def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
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(ADD32ri GR32:$src1, tconstpool:$src2)>;
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@ -3798,11 +3799,15 @@ def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
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(ADD32ri GR32:$src1, tglobaladdr:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
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(ADD32ri GR32:$src1, texternalsym:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
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(ADD32ri GR32:$src1, tblockaddress:$src2)>;
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def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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(MOV32mi addr:$dst, tglobaladdr:$src)>;
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def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV32mi addr:$dst, texternalsym:$src)>;
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def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
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(MOV32mi addr:$dst, tblockaddress:$src)>;
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// Calls
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// tailcall stuff
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