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Pattern ISel: fix argument loading for i64s (thanks chris)
Simple ISel: fix i64 subtract git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20903 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2389,7 +2389,7 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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unsigned DestReg) {
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// Arithmetic and Bitwise operators
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static const unsigned OpcodeTab[] = {
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PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
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PPC::ADD, PPC::SUBF, PPC::AND, PPC::OR, PPC::XOR
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};
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static const unsigned LongOpTab[2][5] = {
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{ PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
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@ -2444,6 +2444,17 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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unsigned Op0r = getReg(Op0, MBB, IP);
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unsigned Op1r = getReg(Op1, MBB, IP);
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// Subtracts have their operands swapped
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if (OperatorClass == 1) {
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if (Class != cLong) {
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BuildMI(*MBB, IP, PPC::SUBF, 2, DestReg).addReg(Op1r).addReg(Op0r);
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} else {
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BuildMI(*MBB, IP, PPC::SUBFC, 2, DestReg+1).addReg(Op1r+1).addReg(Op0r+1);
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BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(Op1r).addReg(Op0r);
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}
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return;
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}
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if (Class != cLong) {
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unsigned Opcode = OpcodeTab[OperatorClass];
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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@ -3876,7 +3887,7 @@ void PPC32ISel::visitAllocaInst(AllocaInst &I) {
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.addImm(0).addImm(27);
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
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BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(AlignedSize).addReg(PPC::R1);
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// Put a pointer to the space into the result register, by copying
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// the stack pointer.
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@ -120,14 +120,10 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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ObjSize = 4;
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if (GPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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unsigned virtReg =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
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argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
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argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
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DAG.getRoot());
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if (ObjectVT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
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argVR.push_back(virtReg);
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argPR.push_back(GPR[GPR_idx]);
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argOp.push_back(PPC::OR);
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} else {
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needsLoad = true;
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}
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@ -137,25 +133,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (GPR_remaining > 1) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
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SDOperand root = DAG.getRoot();
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
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root, DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
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root, DAG.getConstant(0, MVT::i32));
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// Create the pair of virtual registers
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
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unsigned virtReg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
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// Copy the extracted halves into the virtual registers
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SDOperand argHi = DAG.getCopyFromReg(virtReg, MVT::i32, Hi);
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SDOperand argLo = DAG.getCopyFromReg(virtReg+1, MVT::i32, Lo);
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SDOperand argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
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DAG.getRoot());
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SDOperand argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
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// Build the outgoing arg thingy
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argt = newroot = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
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argVR.push_back(virtReg); argVR.push_back(virtReg+1);
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argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
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argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
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argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
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newroot = argLo;
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} else {
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needsLoad = true;
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}
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@ -164,12 +148,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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case MVT::f64: ObjSize = 8;
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if (FPR_remaining > 0) {
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BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
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unsigned virtReg =
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MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
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argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
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argVR.push_back(virtReg);
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argPR.push_back(FPR[FPR_idx]);
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argOp.push_back(PPC::FMR);
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argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
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DAG.getRoot());
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--FPR_remaining;
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++FPR_idx;
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} else {
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@ -199,13 +179,6 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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ArgValues.push_back(argt);
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}
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for (int i = 0, count = argVR.size(); i < count; ++i) {
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if (argOp[i] == PPC::FMR)
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BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
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else
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BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg())
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@ -1014,11 +987,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
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InVals.push_back(SelectExpr(N.getOperand(i)));
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if (N.getOpcode() == ISD::ADD_PARTS) {
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BuildMI(BB, PPC::ADDC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
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BuildMI(BB, PPC::ADDE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::ADDC, 2, Result+1).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::ADDE, 2, Result).addReg(InVals[1]).addReg(InVals[3]);
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} else {
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BuildMI(BB, PPC::SUBFC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
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BuildMI(BB, PPC::SUBFE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::SUBFC, 2, Result+1).addReg(InVals[2]).addReg(InVals[0]);
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BuildMI(BB, PPC::SUBFE, 2, Result).addReg(InVals[3]).addReg(InVals[1]);
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}
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return Result+N.ResNo;
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}
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