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https://github.com/c64scene-ar/llvm-6502.git
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* fp to sint patterns.
* fiadd, fisub, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25189 91177308-0d34-0410-b5e6-96231b3b80d8
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Evan Cheng
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aaca22ca91
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f710062bfb
@ -320,46 +320,58 @@ static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
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// concrete X86 instruction which uses the register stack.
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//
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static const TableEntry OpcodeTable[] = {
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{ X86::FpABS , X86::FABS },
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{ X86::FpADD32m , X86::FADD32m },
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{ X86::FpADD64m , X86::FADD64m },
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{ X86::FpCHS , X86::FCHS },
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{ X86::FpCMOVA , X86::FCMOVA },
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{ X86::FpCMOVAE , X86::FCMOVAE },
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{ X86::FpCMOVB , X86::FCMOVB },
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{ X86::FpCMOVBE , X86::FCMOVBE },
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{ X86::FpCMOVE , X86::FCMOVE },
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{ X86::FpCMOVNE , X86::FCMOVNE },
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{ X86::FpCMOVNP , X86::FCMOVNP },
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{ X86::FpCMOVP , X86::FCMOVP },
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{ X86::FpCOS , X86::FCOS },
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{ X86::FpDIV32m , X86::FDIV32m },
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{ X86::FpDIV64m , X86::FDIV64m },
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{ X86::FpDIVR32m, X86::FDIVR32m },
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{ X86::FpDIVR64m, X86::FDIVR64m },
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{ X86::FpILD16m , X86::FILD16m },
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{ X86::FpILD32m , X86::FILD32m },
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{ X86::FpILD64m , X86::FILD64m },
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{ X86::FpIST16m , X86::FIST16m },
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{ X86::FpIST32m , X86::FIST32m },
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{ X86::FpIST64m , X86::FISTP64m },
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{ X86::FpLD0 , X86::FLD0 },
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{ X86::FpLD1 , X86::FLD1 },
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{ X86::FpLD32m , X86::FLD32m },
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{ X86::FpLD64m , X86::FLD64m },
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{ X86::FpMUL32m , X86::FMUL32m },
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{ X86::FpMUL64m , X86::FMUL64m },
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{ X86::FpSIN , X86::FSIN },
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{ X86::FpSQRT , X86::FSQRT },
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{ X86::FpST32m , X86::FST32m },
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{ X86::FpST64m , X86::FST64m },
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{ X86::FpSUB32m , X86::FSUB32m },
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{ X86::FpSUB64m , X86::FSUB64m },
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{ X86::FpSUBR32m, X86::FSUBR32m },
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{ X86::FpSUBR64m, X86::FSUBR64m },
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{ X86::FpTST , X86::FTST },
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{ X86::FpUCOMIr , X86::FUCOMIr },
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{ X86::FpUCOMr , X86::FUCOMr },
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{ X86::FpABS , X86::FABS },
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{ X86::FpADD32m , X86::FADD32m },
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{ X86::FpADD64m , X86::FADD64m },
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{ X86::FpCHS , X86::FCHS },
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{ X86::FpCMOVA , X86::FCMOVA },
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{ X86::FpCMOVAE , X86::FCMOVAE },
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{ X86::FpCMOVB , X86::FCMOVB },
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{ X86::FpCMOVBE , X86::FCMOVBE },
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{ X86::FpCMOVE , X86::FCMOVE },
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{ X86::FpCMOVNE , X86::FCMOVNE },
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{ X86::FpCMOVNP , X86::FCMOVNP },
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{ X86::FpCMOVP , X86::FCMOVP },
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{ X86::FpCOS , X86::FCOS },
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{ X86::FpDIV32m , X86::FDIV32m },
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{ X86::FpDIV64m , X86::FDIV64m },
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{ X86::FpDIVR32m , X86::FDIVR32m },
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{ X86::FpDIVR64m , X86::FDIVR64m },
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{ X86::FpIADD16m , X86::FIADD16m },
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{ X86::FpIADD32m , X86::FIADD32m },
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{ X86::FpIDIV16m , X86::FIDIV16m },
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{ X86::FpIDIV32m , X86::FIDIV32m },
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{ X86::FpIDIVR16m, X86::FIDIVR16m},
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{ X86::FpIDIVR32m, X86::FIDIVR32m},
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{ X86::FpILD16m , X86::FILD16m },
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{ X86::FpILD32m , X86::FILD32m },
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{ X86::FpILD64m , X86::FILD64m },
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{ X86::FpIMUL16m , X86::FIMUL16m },
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{ X86::FpIMUL32m , X86::FIMUL32m },
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{ X86::FpIST16m , X86::FIST16m },
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{ X86::FpIST32m , X86::FIST32m },
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{ X86::FpIST64m , X86::FISTP64m },
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{ X86::FpISUB16m , X86::FISUB16m },
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{ X86::FpISUB32m , X86::FISUB32m },
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{ X86::FpISUBR16m, X86::FISUBR16m},
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{ X86::FpISUBR32m, X86::FISUBR32m},
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{ X86::FpLD0 , X86::FLD0 },
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{ X86::FpLD1 , X86::FLD1 },
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{ X86::FpLD32m , X86::FLD32m },
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{ X86::FpLD64m , X86::FLD64m },
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{ X86::FpMUL32m , X86::FMUL32m },
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{ X86::FpMUL64m , X86::FMUL64m },
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{ X86::FpSIN , X86::FSIN },
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{ X86::FpSQRT , X86::FSQRT },
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{ X86::FpST32m , X86::FST32m },
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{ X86::FpST64m , X86::FST64m },
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{ X86::FpSUB32m , X86::FSUB32m },
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{ X86::FpSUB64m , X86::FSUB64m },
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{ X86::FpSUBR32m , X86::FSUBR32m },
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{ X86::FpSUBR64m , X86::FSUBR64m },
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{ X86::FpTST , X86::FTST },
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{ X86::FpUCOMIr , X86::FUCOMIr },
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{ X86::FpUCOMr , X86::FUCOMr },
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};
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static unsigned getConcreteOpcode(unsigned Opcode) {
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@ -50,6 +50,7 @@ def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fild64m : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisPtrTy<1>]>;
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def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
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@ -95,6 +96,8 @@ def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain]>;
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def X86fild64m : SDNode<"X86ISD::FILD64m", SDTX86Fild64m,
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[SDNPHasChain]>;
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def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
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[SDNPHasChain, SDNPOutFlag]>;
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@ -2633,19 +2636,67 @@ def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
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def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
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// FIXME: Implement these when we have a dag-dag isel!
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//def FIADD16m : FPI<0xDE, MRM0m>; // ST(0) = ST(0) + [mem16int]
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//def FIADD32m : FPI<0xDA, MRM0m>; // ST(0) = ST(0) + [mem32int]
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//def FIMUL16m : FPI<0xDE, MRM1m>; // ST(0) = ST(0) * [mem16]
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//def FIMUL32m : FPI<0xDA, MRM1m>; // ST(0) = ST(0) * [mem32]
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//def FISUB16m : FPI<0xDE, MRM4m>; // ST(0) = ST(0) - [mem16int]
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//def FISUB32m : FPI<0xDA, MRM4m>; // ST(0) = ST(0) - [mem32int]
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//def FISUBR16m : FPI<0xDE, MRM5m>; // ST(0) = [mem16int] - ST(0)
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//def FISUBR32m : FPI<0xDA, MRM5m>; // ST(0) = [mem32int] - ST(0)
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//def FIDIV16m : FPI<0xDE, MRM6m>; // ST(0) = ST(0) / [mem16int]
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//def FIDIV32m : FPI<0xDA, MRM6m>; // ST(0) = ST(0) / [mem32int]
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//def FIDIVR16m : FPI<0xDE, MRM7m>; // ST(0) = [mem16int] / ST(0)
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//def FIDIVR32m : FPI<0xDA, MRM7m>; // ST(0) = [mem32int] / ST(0)
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def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fadd RFP:$src1,
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(sint_to_fp (loadi16 addr:$src2))))]>;
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// ST(0) = ST(0) + [mem16int]
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def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fadd RFP:$src1,
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(sint_to_fp (loadi32 addr:$src2))))]>;
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// ST(0) = ST(0) + [mem32int]
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def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fmul RFP:$src1,
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(sint_to_fp (loadi16 addr:$src2))))]>;
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// ST(0) = ST(0) * [mem16int]
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def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fmul RFP:$src1,
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(sint_to_fp (loadi32 addr:$src2))))]>;
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// ST(0) = ST(0) * [mem32int]
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def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fsub RFP:$src1,
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(sint_to_fp (loadi16 addr:$src2))))]>;
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// ST(0) = ST(0) - [mem16int]
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def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fsub RFP:$src1,
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(sint_to_fp (loadi32 addr:$src2))))]>;
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// ST(0) = ST(0) - [mem32int]
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def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fsub (sint_to_fp (loadi16 addr:$src2)),
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RFP:$src1))]>;
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// ST(0) = [mem16int] - ST(0)
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def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fsub (sint_to_fp (loadi32 addr:$src2)),
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RFP:$src1))]>;
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// ST(0) = [mem32int] - ST(0)
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def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fdiv RFP:$src1,
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(sint_to_fp (loadi16 addr:$src2))))]>;
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// ST(0) = ST(0) / [mem16int]
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def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fdiv RFP:$src1,
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(sint_to_fp (loadi32 addr:$src2))))]>;
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// ST(0) = ST(0) / [mem32int]
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def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fdiv (sint_to_fp (loadi16 addr:$src2)),
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RFP:$src1))]>;
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// ST(0) = [mem16int] / ST(0)
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def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fdiv (sint_to_fp (loadi32 addr:$src2)),
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RFP:$src1))]>;
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// ST(0) = [mem32int] / ST(0)
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def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
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def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
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def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
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def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
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def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
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def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
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def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
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def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
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def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
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def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{s} $src">;
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def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
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def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{s} $src">;
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// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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@ -2743,11 +2794,11 @@ def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP,
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def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
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[(set RFP:$dst, (loadf64 addr:$src))]>;
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def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
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[]>;
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[(set RFP:$dst, (sint_to_fp (loadi16 addr:$src)))]>;
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def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
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[]>;
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[(set RFP:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
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def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
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[]>;
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[(set RFP:$dst, (X86fild64m addr:$src))]>;
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def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
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[(truncstore RFP:$src, addr:$op, f32)]>;
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