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Instead of adding dependence edges between terminator instructions

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and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.

Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-01-16 22:10:20 +00:00
parent 49bb50e0b6
commit f7119393a9
7 changed files with 70 additions and 26 deletions
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lib/CodeGen/ScheduleDAGEmit.cpp
+3 -3
View File
@@ -33,7 +33,7 @@ void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
}
void ScheduleDAG::EmitNoop() {
TII->insertNoop(*BB, BB->end());
TII->insertNoop(*BB, End);
}
void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
@@ -54,7 +54,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
break;
}
}
TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
TII->copyRegToReg(*BB, End, Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@ -63,7 +63,7 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
TII->copyRegToReg(*BB, BB->end(), VRBase, I->getReg(),
TII->copyRegToReg(*BB, End, VRBase, I->getReg(),
SU->CopyDstRC, SU->CopySrcRC);
}
break;