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[ARM] Small refactor of tryConvertingToTwoOperandForm (nfc)
Also, add more Thumb2 ADD tests requested during review of http://reviews.llvm.org/D11053. Differential Revision: http://reviews.llvm.org/D11130 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242034 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Douglass
parent
5b50110192
commit
f716895679
@ -5477,18 +5477,21 @@ void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
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if (Operands.size() != 6)
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return;
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ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
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ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
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const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
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auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
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if (!Op3.isReg() || !Op4.isReg())
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return;
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auto Op3Reg = Op3.getReg();
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auto Op4Reg = Op4.getReg();
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// For most Thumb2 cases we just generate the 3 operand form and reduce
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// it in processInstruction(), but for ADD involving PC the the 3 operand
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// form won't accept PC so we do the transformation here.
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ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
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auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
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if (isThumbTwo()) {
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if (Mnemonic != "add" ||
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!(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
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!(Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
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(Op5.isReg() && Op5.getReg() == ARM::PC)))
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return;
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} else if (!isThumbOne())
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@ -5503,15 +5506,15 @@ void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
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// If first 2 operands of a 3 operand instruction are the same
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// then transform to 2 operand version of the same instruction
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// e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
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bool Transform = Op3.getReg() == Op4.getReg();
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bool Transform = Op3Reg == Op4Reg;
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// For communtative operations, we might be able to transform if we swap
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// Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
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// as tADDrsp.
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const ARMOperand *LastOp = &Op5;
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bool Swap = false;
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if (!Transform && Op5.isReg() && Op3.getReg() == Op5.getReg() &&
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((Mnemonic == "add" && Op4.getReg() != ARM::SP) ||
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if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
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((Mnemonic == "add" && Op4Reg != ARM::SP) ||
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Mnemonic == "and" || Mnemonic == "eor" ||
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Mnemonic == "adc" || Mnemonic == "orr")) {
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Swap = true;
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@ -49,7 +49,6 @@ _func:
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adcs r0, r1, r3, lsl #7
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adc.w r0, r1, r3, lsr #31
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adcs.w r0, r1, r3, asr #32
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add r2, sp, ip
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@ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
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@ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
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@ -59,7 +58,6 @@ _func:
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@ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10]
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@ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70]
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@ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00]
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@ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
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@------------------------------------------------------------------------------
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@ -115,23 +113,99 @@ _func:
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@------------------------------------------------------------------------------
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@ ADD (register)
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@ ADD (register, not SP) A8.8.6
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@------------------------------------------------------------------------------
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add r1, r2, r8
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add r5, r9, r2, asr #32
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adds r7, r3, r1, lsl #31
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adds.w r0, r3, r6, lsr #25
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add.w r4, r8, r1, ror #12
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adds r1, r1, r7 // T1
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it eq
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addeq r1, r3, r5 // T1
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it eq
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addeq r1, r1, r5 // T1
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it eq
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addseq r1, r3, r5 // T3
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it eq
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addseq r1, r1, r5 // T3
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add r10, r8
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add r10, r10, r8
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it eq
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addeq r1, r10 // T2
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it eq
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addseq r1, r10 // T3
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@ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01]
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@ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05]
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@ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77]
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@ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60]
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@ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34]
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@ CHECK: adds r1, r1, r7 @ encoding: [0xc9,0x19]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addeq r1, r3, r5 @ encoding: [0x59,0x19]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addeq r1, r1, r5 @ encoding: [0x49,0x19]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addseq.w r1, r3, r5 @ encoding: [0x13,0xeb,0x05,0x01]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addseq.w r1, r1, r5 @ encoding: [0x11,0xeb,0x05,0x01]
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@ CHECK: add r10, r8 @ encoding: [0xc2,0x44]
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@ CHECK: add r10, r8 @ encoding: [0xc2,0x44]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addeq r1, r10 @ encoding: [0x51,0x44]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: addseq.w r1, r1, r10 @ encoding: [0x11,0xeb,0x0a,0x01]
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@------------------------------------------------------------------------------
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@ ADD (SP plus immediate) A8.8.9
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@------------------------------------------------------------------------------
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq r7, sp, #1020 // T1
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@ CHECK: addeq r7, sp, #1020 @ encoding: [0xff,0xaf]
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq sp, sp, #508 // T2
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@ FIXME: ARMARM says 'addeq sp, sp, #508'
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@ CHECK: addeq sp, #508 @ encoding: [0x7f,0xb0]
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add r7, sp, #15 // T3
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@ CHECK: add.w r7, sp, #15 @ encoding: [0x0d,0xf1,0x0f,0x07]
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adds r7, sp, #16 // T3
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@ CHECK: adds.w r7, sp, #16 @ encoding: [0x1d,0xf1,0x10,0x07]
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add r8, sp, #16 // T3
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@ CHECK: add.w r8, sp, #16 @ encoding: [0x0d,0xf1,0x10,0x08]
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addw r6, sp, #1020 // T4
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@ CHECK: addw r6, sp, #1020 @ encoding: [0x0d,0xf2,0xfc,0x36]
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add r6, sp, #1019 // T4
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@ CHECK: addw r6, sp, #1019 @ encoding: [0x0d,0xf2,0xfb,0x36]
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@------------------------------------------------------------------------------
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@ ADD (SP plus register) A8.8.10
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@------------------------------------------------------------------------------
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq r8, sp, r8 // T1
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@ CHECK: addeq r8, sp, r8 @ encoding: [0xe8,0x44]
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq r8, sp // T1
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@ CHECK: addeq r8, sp @ encoding: [0xe8,0x44]
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq sp, r9 // T2
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@ CHECK: addeq sp, r9 @ encoding: [0xcd,0x44]
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add r2, sp, ip // T3
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@ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
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it eq
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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addeq r2, sp, ip // T3
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@ CHECK: addeq.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
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@------------------------------------------------------------------------------
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