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revert part of the last change, should fix regressions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23241 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -131,9 +131,9 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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MachineBasicBlock& BB = MF.front();
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std::vector<SDOperand> ArgValues;
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static const unsigned args_int[] = {
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unsigned args_int[] = {
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Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
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static const unsigned args_float[] = {
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unsigned args_float[] = {
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Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
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unsigned added_int = 0;
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unsigned added_fp = 0;
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@ -155,7 +155,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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abort();
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case MVT::f64:
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case MVT::f32:
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MF.addLiveIn(args_float[count]);
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args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
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added_fp |= (1 << count);
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
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DAG.setRoot(argt.getValue(1));
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@ -165,7 +165,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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MF.addLiveIn(args_int[count]);
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args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
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added_int |= (1 << count);
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
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DAG.setRoot(argt.getValue(1));
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@ -198,7 +198,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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std::vector<SDOperand> LS;
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for (int i = 0; i < 6; ++i) {
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if (!(added_int & (1 << i)))
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MF.addLiveIn(args_int[i]);
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args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
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SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
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int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
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if (i == 0) VarArgsBase = FI;
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@ -207,7 +207,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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SDFI, DAG.getSrcValue(NULL)));
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if (!(added_fp & (1 << i)))
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MF.addLiveIn(args_float[i]);
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args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
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FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
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SDFI = DAG.getFrameIndex(FI, MVT::i64);
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@ -1733,6 +1733,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
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return Result;
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}
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case ISD::AssertSext:
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case ISD::AssertZext:
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return SelectExpr(N.getOperand(0));
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}
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return 0;
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