mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e3087890ac
commit
f73823000e
@ -233,7 +233,7 @@ public:
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
Removed = true;
|
||||
break;
|
||||
}
|
||||
@ -278,7 +278,7 @@ public:
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
|
||||
MO.unsetIsDead();
|
||||
MO.setIsDead(false);
|
||||
Removed = true;
|
||||
break;
|
||||
}
|
||||
|
@ -21,7 +21,6 @@
|
||||
namespace llvm {
|
||||
|
||||
class TargetInstrDescriptor;
|
||||
class TargetMachine;
|
||||
|
||||
template <typename T> struct ilist_traits;
|
||||
template <typename T> struct ilist;
|
||||
|
@ -23,7 +23,8 @@ namespace llvm {
|
||||
|
||||
class MachineBasicBlock;
|
||||
class GlobalValue;
|
||||
class MachineInstr;
|
||||
class MachineInstr;
|
||||
class TargetMachine;
|
||||
|
||||
/// MachineOperand class - Representation of each machine instruction operand.
|
||||
///
|
||||
@ -77,9 +78,6 @@ private:
|
||||
|
||||
MachineOperand() : ParentMI(0) {}
|
||||
|
||||
void print(std::ostream &os) const;
|
||||
void print(std::ostream *os) const { if (os) print(*os); }
|
||||
|
||||
public:
|
||||
MachineOperand(const MachineOperand &M) {
|
||||
*this = M;
|
||||
@ -96,6 +94,8 @@ public:
|
||||
MachineInstr *getParent() { return ParentMI; }
|
||||
const MachineInstr *getParent() const { return ParentMI; }
|
||||
|
||||
void print(std::ostream &os, const TargetMachine *TM = 0) const;
|
||||
|
||||
/// Accessors that tell you what kind of MachineOperand you're looking at.
|
||||
///
|
||||
bool isRegister() const { return opType == MO_Register; }
|
||||
@ -107,6 +107,90 @@ public:
|
||||
bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
|
||||
bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Accessors for Register Operands
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
/// getReg - Returns the register number.
|
||||
unsigned getReg() const {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
return contents.RegNo;
|
||||
}
|
||||
|
||||
unsigned getSubReg() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return (unsigned)SubReg;
|
||||
}
|
||||
|
||||
bool isUse() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return !IsDef;
|
||||
}
|
||||
|
||||
bool isDef() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDef;
|
||||
}
|
||||
|
||||
bool isImplicit() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsImp;
|
||||
}
|
||||
|
||||
bool isDead() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDead;
|
||||
}
|
||||
|
||||
bool isKill() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsKill;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Mutators for Register Operands
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
void setReg(unsigned Reg) {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
contents.RegNo = Reg;
|
||||
}
|
||||
|
||||
void setSubReg(unsigned subReg) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
SubReg = (unsigned char)subReg;
|
||||
}
|
||||
|
||||
void setIsUse(bool Val = true) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = !Val;
|
||||
}
|
||||
|
||||
void setIsDef(bool Val = true) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = Val;
|
||||
}
|
||||
|
||||
void setImplicit(bool Val = true) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsImp = Val;
|
||||
}
|
||||
|
||||
void setIsKill(bool Val = true) {
|
||||
assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
|
||||
IsKill = Val;
|
||||
}
|
||||
|
||||
void setIsDead(bool Val = true) {
|
||||
assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
|
||||
IsDead = Val;
|
||||
}
|
||||
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Accessors for various operand types.
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
int64_t getImm() const {
|
||||
assert(isImmediate() && "Wrong MachineOperand accessor");
|
||||
return contents.ImmVal;
|
||||
@ -142,83 +226,18 @@ public:
|
||||
}
|
||||
int getOffset() const {
|
||||
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
|
||||
"Wrong MachineOperand accessor");
|
||||
"Wrong MachineOperand accessor");
|
||||
return auxInfo.offset;
|
||||
}
|
||||
unsigned getSubReg() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return (unsigned)SubReg;
|
||||
}
|
||||
const char *getSymbolName() const {
|
||||
assert(isExternalSymbol() && "Wrong MachineOperand accessor");
|
||||
return contents.SymbolName;
|
||||
}
|
||||
|
||||
bool isUse() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return !IsDef;
|
||||
}
|
||||
bool isDef() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDef;
|
||||
}
|
||||
void setIsUse() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = false;
|
||||
}
|
||||
void setIsDef() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsDef = true;
|
||||
}
|
||||
|
||||
bool isImplicit() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsImp;
|
||||
}
|
||||
void setImplicit() {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
IsImp = true;
|
||||
}
|
||||
|
||||
bool isKill() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsKill;
|
||||
}
|
||||
bool isDead() const {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
return IsDead;
|
||||
}
|
||||
void setIsKill() {
|
||||
assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
|
||||
IsKill = true;
|
||||
}
|
||||
void setIsDead() {
|
||||
assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
|
||||
IsDead = true;
|
||||
}
|
||||
void unsetIsKill() {
|
||||
assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
|
||||
IsKill = false;
|
||||
}
|
||||
void unsetIsDead() {
|
||||
assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
|
||||
IsDead = false;
|
||||
}
|
||||
|
||||
/// getReg - Returns the register number.
|
||||
///
|
||||
unsigned getReg() const {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
return contents.RegNo;
|
||||
}
|
||||
|
||||
/// MachineOperand mutators.
|
||||
///
|
||||
void setReg(unsigned Reg) {
|
||||
assert(isRegister() && "This is not a register operand!");
|
||||
contents.RegNo = Reg;
|
||||
}
|
||||
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Mutators for various operand types.
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
void setImm(int64_t immVal) {
|
||||
assert(isImmediate() && "Wrong MachineOperand mutator");
|
||||
contents.ImmVal = immVal;
|
||||
@ -229,19 +248,21 @@ public:
|
||||
"Wrong MachineOperand accessor");
|
||||
auxInfo.offset = Offset;
|
||||
}
|
||||
void setSubReg(unsigned subReg) {
|
||||
assert(isRegister() && "Wrong MachineOperand accessor");
|
||||
SubReg = (unsigned char)subReg;
|
||||
}
|
||||
|
||||
void setConstantPoolIndex(unsigned Idx) {
|
||||
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
|
||||
contents.Index = Idx;
|
||||
}
|
||||
|
||||
void setJumpTableIndex(unsigned Idx) {
|
||||
assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
|
||||
contents.Index = Idx;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Other methods.
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
/// isIdenticalTo - Return true if this operand is identical to the specified
|
||||
/// operand. Note: This method ignores isKill and isDead properties.
|
||||
bool isIdenticalTo(const MachineOperand &Other) const;
|
||||
@ -268,12 +289,17 @@ public:
|
||||
SubReg = 0;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Construction methods.
|
||||
//===--------------------------------------------------------------------===//
|
||||
|
||||
static MachineOperand CreateImm(int64_t Val) {
|
||||
MachineOperand Op;
|
||||
Op.opType = MachineOperand::MO_Immediate;
|
||||
Op.contents.ImmVal = Val;
|
||||
return Op;
|
||||
}
|
||||
|
||||
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
||||
bool isKill = false, bool isDead = false,
|
||||
unsigned SubReg = 0) {
|
||||
@ -339,15 +365,13 @@ public:
|
||||
return *this;
|
||||
}
|
||||
|
||||
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
|
||||
mop.print(os);
|
||||
return os;
|
||||
}
|
||||
|
||||
friend class MachineInstr;
|
||||
};
|
||||
|
||||
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
|
||||
inline std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
|
||||
MO.print(OS, 0);
|
||||
return OS;
|
||||
}
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
|
@ -1213,7 +1213,7 @@ addIntervalsForSpills(const LiveInterval &li,
|
||||
assert(KillMI && "Last use disappeared?");
|
||||
int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true);
|
||||
assert(KillOp != -1 && "Last use disappeared?");
|
||||
KillMI->getOperand(KillOp).unsetIsKill();
|
||||
KillMI->getOperand(KillOp).setIsKill(false);
|
||||
}
|
||||
vrm.removeKillPoint(li.reg);
|
||||
bool DefIsReMat = vrm.isReMaterialized(li.reg);
|
||||
|
@ -608,7 +608,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI,
|
||||
VarInfo &VI = getVarInfo(Reg);
|
||||
if (MO.isDef()) {
|
||||
if (MO.isDead()) {
|
||||
MO.unsetIsDead();
|
||||
MO.setIsDead(false);
|
||||
addVirtualRegisterDead(Reg, NewMI);
|
||||
}
|
||||
// Update the defining instruction.
|
||||
@ -616,7 +616,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI,
|
||||
VI.DefInst = NewMI;
|
||||
}
|
||||
if (MO.isKill()) {
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
addVirtualRegisterKilled(Reg, NewMI);
|
||||
}
|
||||
// If this is a kill of the value, update the VI kills list.
|
||||
@ -640,12 +640,12 @@ void LiveVariables::transferKillDeadInfo(MachineInstr *OldMI,
|
||||
unsigned Reg = MO.getReg();
|
||||
if (MO.isDef()) {
|
||||
if (MO.isDead()) {
|
||||
MO.unsetIsDead();
|
||||
MO.setIsDead(false);
|
||||
addRegisterDead(Reg, NewMI, RegInfo);
|
||||
}
|
||||
}
|
||||
if (MO.isKill()) {
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
addRegisterKilled(Reg, NewMI, RegInfo);
|
||||
}
|
||||
}
|
||||
@ -659,7 +659,7 @@ void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isKill()) {
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
unsigned Reg = MO.getReg();
|
||||
if (MRegisterInfo::isVirtualRegister(Reg)) {
|
||||
bool removed = getVarInfo(Reg).removeKill(MI);
|
||||
@ -675,7 +675,7 @@ void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isDead()) {
|
||||
MO.unsetIsDead();
|
||||
MO.setIsDead(false);
|
||||
unsigned Reg = MO.getReg();
|
||||
if (MRegisterInfo::isVirtualRegister(Reg)) {
|
||||
bool removed = getVarInfo(Reg).removeKill(MI);
|
||||
|
@ -21,6 +21,118 @@
|
||||
#include <ostream>
|
||||
using namespace llvm;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MachineOperand Implementation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// isIdenticalTo - Return true if this operand is identical to the specified
|
||||
/// operand.
|
||||
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
|
||||
if (getType() != Other.getType()) return false;
|
||||
|
||||
switch (getType()) {
|
||||
default: assert(0 && "Unrecognized operand type");
|
||||
case MachineOperand::MO_Register:
|
||||
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
|
||||
getSubReg() == Other.getSubReg();
|
||||
case MachineOperand::MO_Immediate:
|
||||
return getImm() == Other.getImm();
|
||||
case MachineOperand::MO_MachineBasicBlock:
|
||||
return getMBB() == Other.getMBB();
|
||||
case MachineOperand::MO_FrameIndex:
|
||||
return getFrameIndex() == Other.getFrameIndex();
|
||||
case MachineOperand::MO_ConstantPoolIndex:
|
||||
return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
|
||||
getOffset() == Other.getOffset();
|
||||
case MachineOperand::MO_JumpTableIndex:
|
||||
return getJumpTableIndex() == Other.getJumpTableIndex();
|
||||
case MachineOperand::MO_GlobalAddress:
|
||||
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
|
||||
case MachineOperand::MO_ExternalSymbol:
|
||||
return !strcmp(getSymbolName(), Other.getSymbolName()) &&
|
||||
getOffset() == Other.getOffset();
|
||||
}
|
||||
}
|
||||
|
||||
/// print - Print the specified machine operand.
|
||||
///
|
||||
void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
|
||||
switch (getType()) {
|
||||
case MachineOperand::MO_Register:
|
||||
if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
|
||||
OS << "%reg" << getReg();
|
||||
} else {
|
||||
// If the instruction is embedded into a basic block, we can find the
|
||||
// target
|
||||
// info for the instruction.
|
||||
if (TM == 0)
|
||||
if (const MachineInstr *MI = getParent())
|
||||
if (const MachineBasicBlock *MBB = MI->getParent())
|
||||
if (const MachineFunction *MF = MBB->getParent())
|
||||
TM = &MF->getTarget();
|
||||
|
||||
if (TM)
|
||||
OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
|
||||
else
|
||||
OS << "%mreg" << getReg();
|
||||
}
|
||||
|
||||
if (isDef() || isKill() || isDead() || isImplicit()) {
|
||||
OS << "<";
|
||||
bool NeedComma = false;
|
||||
if (isImplicit()) {
|
||||
OS << (isDef() ? "imp-def" : "imp-use");
|
||||
NeedComma = true;
|
||||
} else if (isDef()) {
|
||||
OS << "def";
|
||||
NeedComma = true;
|
||||
}
|
||||
if (isKill() || isDead()) {
|
||||
if (NeedComma) OS << ",";
|
||||
if (isKill()) OS << "kill";
|
||||
if (isDead()) OS << "dead";
|
||||
}
|
||||
OS << ">";
|
||||
}
|
||||
break;
|
||||
case MachineOperand::MO_Immediate:
|
||||
OS << getImm();
|
||||
break;
|
||||
case MachineOperand::MO_MachineBasicBlock:
|
||||
OS << "mbb<"
|
||||
<< ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
|
||||
<< "," << (void*)getMachineBasicBlock() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_FrameIndex:
|
||||
OS << "<fi#" << getFrameIndex() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_ConstantPoolIndex:
|
||||
OS << "<cp#" << getConstantPoolIndex();
|
||||
if (getOffset()) OS << "+" << getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
case MachineOperand::MO_JumpTableIndex:
|
||||
OS << "<jt#" << getJumpTableIndex() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_GlobalAddress:
|
||||
OS << "<ga:" << ((Value*)getGlobal())->getName();
|
||||
if (getOffset()) OS << "+" << getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
case MachineOperand::MO_ExternalSymbol:
|
||||
OS << "<es:" << getSymbolName();
|
||||
if (getOffset()) OS << "+" << getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
default:
|
||||
assert(0 && "Unrecognized operand type");
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MachineInstr Implementation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
|
||||
/// TID NULL and no operands.
|
||||
MachineInstr::MachineInstr()
|
||||
@ -145,34 +257,6 @@ unsigned MachineInstr::getNumExplicitOperands() const {
|
||||
return NumOperands;
|
||||
}
|
||||
|
||||
/// isIdenticalTo - Return true if this operand is identical to the specified
|
||||
/// operand.
|
||||
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
|
||||
if (getType() != Other.getType()) return false;
|
||||
|
||||
switch (getType()) {
|
||||
default: assert(0 && "Unrecognized operand type");
|
||||
case MachineOperand::MO_Register:
|
||||
return getReg() == Other.getReg() && isDef() == Other.isDef() &&
|
||||
getSubReg() == Other.getSubReg();
|
||||
case MachineOperand::MO_Immediate:
|
||||
return getImm() == Other.getImm();
|
||||
case MachineOperand::MO_MachineBasicBlock:
|
||||
return getMBB() == Other.getMBB();
|
||||
case MachineOperand::MO_FrameIndex:
|
||||
return getFrameIndex() == Other.getFrameIndex();
|
||||
case MachineOperand::MO_ConstantPoolIndex:
|
||||
return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
|
||||
getOffset() == Other.getOffset();
|
||||
case MachineOperand::MO_JumpTableIndex:
|
||||
return getJumpTableIndex() == Other.getJumpTableIndex();
|
||||
case MachineOperand::MO_GlobalAddress:
|
||||
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
|
||||
case MachineOperand::MO_ExternalSymbol:
|
||||
return !strcmp(getSymbolName(), Other.getSymbolName()) &&
|
||||
getOffset() == Other.getOffset();
|
||||
}
|
||||
}
|
||||
|
||||
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
|
||||
/// the specific register or -1 if it is not found. It further tightening
|
||||
@ -267,87 +351,11 @@ void MachineInstr::dump() const {
|
||||
cerr << " " << *this;
|
||||
}
|
||||
|
||||
/// print - Print the specified machine operand.
|
||||
///
|
||||
static void print(const MachineOperand &MO, std::ostream &OS,
|
||||
const TargetMachine *TM) {
|
||||
switch (MO.getType()) {
|
||||
case MachineOperand::MO_Register:
|
||||
if (MO.getReg() == 0 || MRegisterInfo::isVirtualRegister(MO.getReg()))
|
||||
OS << "%reg" << MO.getReg();
|
||||
else {
|
||||
// If the instruction is embedded into a basic block, we can find the
|
||||
// target
|
||||
// info for the instruction.
|
||||
if (TM == 0)
|
||||
if (const MachineInstr *MI = MO.getParent())
|
||||
if (const MachineBasicBlock *MBB = MI->getParent())
|
||||
if (const MachineFunction *MF = MBB->getParent())
|
||||
TM = &MF->getTarget();
|
||||
|
||||
if (TM)
|
||||
OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
|
||||
else
|
||||
OS << "%mreg" << MO.getReg();
|
||||
}
|
||||
|
||||
if (MO.isDef() || MO.isKill() || MO.isDead() || MO.isImplicit()) {
|
||||
OS << "<";
|
||||
bool NeedComma = false;
|
||||
if (MO.isImplicit()) {
|
||||
OS << (MO.isDef() ? "imp-def" : "imp-use");
|
||||
NeedComma = true;
|
||||
} else if (MO.isDef()) {
|
||||
OS << "def";
|
||||
NeedComma = true;
|
||||
}
|
||||
if (MO.isKill() || MO.isDead()) {
|
||||
if (NeedComma) OS << ",";
|
||||
if (MO.isKill()) OS << "kill";
|
||||
if (MO.isDead()) OS << "dead";
|
||||
}
|
||||
OS << ">";
|
||||
}
|
||||
break;
|
||||
case MachineOperand::MO_Immediate:
|
||||
OS << MO.getImm();
|
||||
break;
|
||||
case MachineOperand::MO_MachineBasicBlock:
|
||||
OS << "mbb<"
|
||||
<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
|
||||
<< "," << (void*)MO.getMachineBasicBlock() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_FrameIndex:
|
||||
OS << "<fi#" << MO.getFrameIndex() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_ConstantPoolIndex:
|
||||
OS << "<cp#" << MO.getConstantPoolIndex();
|
||||
if (MO.getOffset()) OS << "+" << MO.getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
case MachineOperand::MO_JumpTableIndex:
|
||||
OS << "<jt#" << MO.getJumpTableIndex() << ">";
|
||||
break;
|
||||
case MachineOperand::MO_GlobalAddress:
|
||||
OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
|
||||
if (MO.getOffset()) OS << "+" << MO.getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
case MachineOperand::MO_ExternalSymbol:
|
||||
OS << "<es:" << MO.getSymbolName();
|
||||
if (MO.getOffset()) OS << "+" << MO.getOffset();
|
||||
OS << ">";
|
||||
break;
|
||||
default:
|
||||
assert(0 && "Unrecognized operand type");
|
||||
}
|
||||
}
|
||||
|
||||
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
|
||||
// Specialize printing if op#0 is definition
|
||||
unsigned StartOp = 0;
|
||||
if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
|
||||
::print(getOperand(0), OS, TM);
|
||||
getOperand(0).print(OS, TM);
|
||||
OS << " = ";
|
||||
++StartOp; // Don't print this operand again!
|
||||
}
|
||||
@ -358,13 +366,9 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
|
||||
if (i != StartOp)
|
||||
OS << ",";
|
||||
OS << " ";
|
||||
::print(getOperand(i), OS, TM);
|
||||
getOperand(i).print(OS, TM);
|
||||
}
|
||||
|
||||
OS << "\n";
|
||||
}
|
||||
|
||||
void MachineOperand::print(std::ostream &OS) const {
|
||||
::print(*this, OS, 0);
|
||||
}
|
||||
|
||||
|
@ -185,7 +185,7 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInte
|
||||
// merge, unset the isKill marker given the live range has been extended.
|
||||
int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
|
||||
if (UIdx != -1)
|
||||
ValLREndInst->getOperand(UIdx).unsetIsKill();
|
||||
ValLREndInst->getOperand(UIdx).setIsKill(false);
|
||||
|
||||
++numPeep;
|
||||
return true;
|
||||
@ -1303,7 +1303,7 @@ void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg)
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isKill() && MO.getReg() &&
|
||||
mri_->regsOverlap(rep(MO.getReg()), Reg))
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1327,7 +1327,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isRegister() && MO.isKill() && MO.getReg() &&
|
||||
mri_->regsOverlap(rep(MO.getReg()), Reg)) {
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -479,7 +479,7 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
|
||||
static void InvalidateKill(unsigned Reg, BitVector &RegKills,
|
||||
std::vector<MachineOperand*> &KillOps) {
|
||||
if (RegKills[Reg]) {
|
||||
KillOps[Reg]->unsetIsKill();
|
||||
KillOps[Reg]->setIsKill(false);
|
||||
KillOps[Reg] = NULL;
|
||||
RegKills.reset(Reg);
|
||||
}
|
||||
@ -547,7 +547,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
|
||||
if (RegKills[Reg]) {
|
||||
// That can't be right. Register is killed but not re-defined and it's
|
||||
// being reused. Let's fix that.
|
||||
KillOps[Reg]->unsetIsKill();
|
||||
KillOps[Reg]->setIsKill(false);
|
||||
KillOps[Reg] = NULL;
|
||||
RegKills.reset(Reg);
|
||||
if (i < TID->numOperands &&
|
||||
|
@ -152,14 +152,8 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
|
||||
bool Reg2IsKill = MI->getOperand(2).isKill();
|
||||
MI->getOperand(2).setReg(Reg1);
|
||||
MI->getOperand(1).setReg(Reg2);
|
||||
if (Reg1IsKill)
|
||||
MI->getOperand(2).setIsKill();
|
||||
else
|
||||
MI->getOperand(2).unsetIsKill();
|
||||
if (Reg2IsKill)
|
||||
MI->getOperand(1).setIsKill();
|
||||
else
|
||||
MI->getOperand(1).unsetIsKill();
|
||||
MI->getOperand(2).setIsKill(Reg1IsKill);
|
||||
MI->getOperand(1).setIsKill(Reg2IsKill);
|
||||
|
||||
// Swap the mask around.
|
||||
unsigned MB = MI->getOperand(4).getImm();
|
||||
|
@ -49,14 +49,8 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
|
||||
bool Reg2IsKill = MI->getOperand(2).isKill();
|
||||
MI->getOperand(2).setReg(Reg1);
|
||||
MI->getOperand(1).setReg(Reg2);
|
||||
if (Reg1IsKill)
|
||||
MI->getOperand(2).setIsKill();
|
||||
else
|
||||
MI->getOperand(2).unsetIsKill();
|
||||
if (Reg2IsKill)
|
||||
MI->getOperand(1).setIsKill();
|
||||
else
|
||||
MI->getOperand(1).unsetIsKill();
|
||||
MI->getOperand(2).setIsKill(Reg1IsKill);
|
||||
MI->getOperand(1).setIsKill(Reg2IsKill);
|
||||
return MI;
|
||||
}
|
||||
|
||||
|
@ -1302,7 +1302,7 @@ bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
||||
for (unsigned i = 1; i != 5; ++i) {
|
||||
MachineOperand &MO = NewMIs[0]->getOperand(i);
|
||||
if (MO.isRegister())
|
||||
MO.unsetIsKill();
|
||||
MO.setIsKill(false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user