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No targets support line number info yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -98,6 +98,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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//Doesn't work yet
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setOperationAction(ISD::SETCC, MVT::f32, Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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computeRegisterProperties();
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addLegalFPImmediate(+0.0); //F31
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@ -72,6 +72,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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//IA64 has these, but they are not implemented
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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@ -91,6 +91,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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// PowerPC does not have truncstore for i1.
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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// PowerPC doesn't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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// We want to legalize GlobalAddress into the appropriate instructions to
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// materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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@ -116,6 +116,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
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