Overhaul memory barriers in the ARM backend. Radar 8601999.

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInfo.h

@@ -101,6 +101,7 @@ namespace ARM_MB {
   // The Memory Barrier Option constants map directly to the 4-bit encoding of
   // the option field for memory barrier operations.
   enum MemBOpt {
+    SY    = 15,
     ST    = 14,
     ISH   = 11,
     ISHST = 10,
@@ -113,6 +114,7 @@ namespace ARM_MB {
   inline static const char *MemBOptToString(unsigned val) {
     switch (val) {
     default: llvm_unreachable("Unknown memory operation");
+    case SY:    return "sy";
     case ST:    return "st";
     case ISH:   return "ish";
     case ISHST: return "ishst";