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Fix loop conditionals (MO.isDef() asserts that it's a reg) and

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move some constraints around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-20 00:36:24 +00:00
parent cb59229a4a
commit f762fbe4fa
1 changed files with 2 additions and 1 deletions
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lib/Target/ARM/ARMFastISel.cpp
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@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
// Look to see if our OptionalDef is defining CPSR or CCR.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR)
if (!MO.isReg() || !MO.isDef()) continue;
if (MO.getReg() == ARM::CPSR)
*CPSR = true;
}
return true;