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https://github.com/c64scene-ar/llvm-6502.git
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ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
@@ -130,6 +130,13 @@ public:
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return true;
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}
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bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
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const ConstantSDNode *CN = cast<ConstantSDNode>(N);
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Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
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return true;
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}
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bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
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@@ -239,21 +246,6 @@ private:
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/// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
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SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
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/// SelectCMOVOp - Select CMOV instructions for ARM.
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SDNode *SelectCMOVOp(SDNode *N);
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SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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// Select special operations if node forms integer ABS pattern
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SDNode *SelectABSOp(SDNode *N);
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@@ -2321,204 +2313,6 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::
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SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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SDValue CPTmp0;
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SDValue CPTmp1;
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if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
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unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
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unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
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unsigned Opc = 0;
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switch (SOShOp) {
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case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
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case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
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case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
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case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
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default:
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llvm_unreachable("Unknown so_reg opcode!");
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}
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SDValue SOShImm =
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CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
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}
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if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (!T)
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return 0;
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unsigned Opc = 0;
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unsigned TrueImm = T->getZExtValue();
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if (is_t2_so_imm(TrueImm)) {
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Opc = ARM::t2MOVCCi;
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} else if (TrueImm <= 0xffff) {
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Opc = ARM::t2MOVCCi16;
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} else if (is_t2_so_imm_not(TrueImm)) {
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TrueImm = ~TrueImm;
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Opc = ARM::t2MVNCCi;
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} else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
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// Large immediate.
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Opc = ARM::t2MOVCCi32imm;
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}
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if (Opc) {
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SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (!T)
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return 0;
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unsigned Opc = 0;
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unsigned TrueImm = T->getZExtValue();
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bool isSoImm = is_so_imm(TrueImm);
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if (isSoImm) {
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Opc = ARM::MOVCCi;
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} else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
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Opc = ARM::MOVCCi16;
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} else if (is_so_imm_not(TrueImm)) {
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TrueImm = ~TrueImm;
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Opc = ARM::MVNCCi;
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} else if (TrueVal.getNode()->hasOneUse() &&
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(Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
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// Large immediate.
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Opc = ARM::MOVCCi32imm;
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}
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if (Opc) {
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SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
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EVT VT = N->getValueType(0);
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SDValue FalseVal = N->getOperand(0);
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SDValue TrueVal = N->getOperand(1);
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SDValue CC = N->getOperand(2);
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SDValue CCR = N->getOperand(3);
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SDValue InFlag = N->getOperand(4);
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assert(CC.getOpcode() == ISD::Constant);
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assert(CCR.getOpcode() == ISD::Register);
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ARMCC::CondCodes CCVal =
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(ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
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if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 18 cost = 1 size = 0
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if (Subtarget->isThumb()) {
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SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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} else {
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SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false,
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// (imm:i32)<<P:Pred_so_imm>>:$true,
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// (imm:i32):$cc)
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// Emits: (MOVCCi:i32 GPR:i32:$false,
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// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
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// Pattern complexity = 10 cost = 1 size = 0
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if (Subtarget->isThumb()) {
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SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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} else {
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SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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}
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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//
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 11 size = 0
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//
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// Also VMOVScc and VMOVDcc.
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SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
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unsigned Opc = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Illegal conditional move type!");
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case MVT::i32:
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Opc = Subtarget->isThumb()
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? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
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: ARM::MOVCCr;
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break;
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case MVT::f32:
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Opc = ARM::VMOVScc;
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break;
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case MVT::f64:
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Opc = ARM::VMOVDcc;
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break;
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}
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return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
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}
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/// Target-specific DAG combining for ISD::XOR.
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/// Target-independent combining lowers SELECT_CC nodes of the form
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/// select_cc setg[ge] X, 0, X, -X
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@@ -2882,8 +2676,6 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDValue(Chain.getNode(), Chain.getResNo()));
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return NULL;
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}
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case ARMISD::CMOV:
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return SelectCMOVOp(N);
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case ARMISD::VZIP: {
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unsigned Opc = 0;
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EVT VT = N->getValueType(0);
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