mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Removed Mr. Smith from the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24070 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fd306bfdd2
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@ -19,72 +19,6 @@
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#include <algorithm>
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using namespace llvm;
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//
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// Convenience types.
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//
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typedef std::vector<Record*> RecordList;
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//
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// RecordListIter - Simplify iterating through a std::vector of records.
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//
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class RecordListIter {
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std::vector<Record*>::iterator RI; // Currect cursor
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std::vector<Record*>::iterator E; // End point
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public:
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//
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// Ctor.
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//
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RecordListIter(RecordList &RL)
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: RI(RL.begin()), E(RL.end())
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{}
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//
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// isMore - Return true if more records are available.
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//
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bool isMore() const { return RI != E; }
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//
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// next - Return the next record or NULL if none.
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//
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Record *next() { return isMore() ? *RI++ : NULL; }
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};
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//
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// DefListIter - Simplify iterating through a field which is a list of records.
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//
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struct DefListIter {
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ListInit *List; // List of DefInit
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unsigned N; // Number of elements in list
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unsigned i; // Current index in list
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//
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// Ctor - Lookup field and get list and length.
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//
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DefListIter(Record *R, const std::string &Name)
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: List(R->getValueAsListInit(Name)), N(List->getSize()), i(0)
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{}
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//
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// isMore - Return true if more records are available.
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//
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bool isMore() const { return i < N; }
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//
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// next - Return the next record or NULL if none.
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//
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Record *next() {
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if (isMore()) {
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if (DefInit *DI = dynamic_cast<DefInit*>(List->getElement(i++))) {
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return DI->getDef();
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}
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}
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return NULL;
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}
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};
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//
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// Record sort by name function.
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//
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@ -110,27 +44,28 @@ void SubtargetEmitter::Enumeration(std::ostream &OS,
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const char *ClassName,
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bool isBits) {
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// Get all records of class and sort
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RecordList Defs = Records.getAllDerivedDefinitions(ClassName);
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sort(Defs.begin(), Defs.end(), LessRecord());
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std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
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sort(DefList.begin(), DefList.end(), LessRecord());
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// Track position if isBits
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int i = 0;
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// Open enumeration
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OS << "enum {\n";
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// For each record
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RecordListIter DI(Defs);
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while (Record *R = DI.next()) {
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for (unsigned i = 0, N = DefList.size(); i < N;) {
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// Next record
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Record *Def = DefList[i];
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// Get and emit name
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std::string Name = R->getName();
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std::string Name = Def->getName();
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OS << " " << Name;
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// If bit flags then emit expression (1 << i)
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if (isBits) OS << " = " << " 1 << " << i++;
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if (isBits) OS << " = " << " 1 << " << i;
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// Depending on if more in the list, emit comma and new line
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OS << (DI.isMore() ? ",\n" : "\n");
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// Depending on if more in the list emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// Close enumeration
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@ -143,26 +78,34 @@ void SubtargetEmitter::Enumeration(std::ostream &OS,
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//
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void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
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// Gather and sort all the features
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RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
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sort(Features.begin(), Features.end(), LessRecord());
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std::vector<Record*> FeatureList =
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Records.getAllDerivedDefinitions("SubtargetFeature");
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sort(FeatureList.begin(), FeatureList.end(), LessRecord());
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// Begin feature table
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OS << "// Sorted (by key) array of values for CPU features.\n"
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<< "static llvm::SubtargetFeatureKV FeatureKV[] = {\n";
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// For each feature
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RecordListIter FI(Features);
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while (Record *R = FI.next()) {
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std::string Instance = R->getName();
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std::string Name = R->getValueAsString("Name");
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std::string Desc = R->getValueAsString("Desc");
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for (unsigned i = 0, N = FeatureList.size(); i < N;) {
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// Next feature
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Record *Feature = FeatureList[i];
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std::string Name = Feature->getName();
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std::string CommandLineName = Feature->getValueAsString("Name");
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std::string Desc = Feature->getValueAsString("Desc");
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// Emit as { "feature", "decription", feactureEnum }
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OS << " { "
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<< "\"" << Name << "\", "
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<< "\"" << CommandLineName << "\", "
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<< "\"" << Desc << "\", "
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<< Instance
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<< (FI.isMore() ? " },\n" : " }\n");
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<< Name
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<< " }";
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// Depending on if more in the list emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// End feature table
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@ -180,35 +123,44 @@ void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
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//
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void SubtargetEmitter::CPUKeyValues(std::ostream &OS) {
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// Gather and sort processor information
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RecordList Processors = Records.getAllDerivedDefinitions("Processor");
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sort(Processors.begin(), Processors.end(), LessRecordFieldName());
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std::vector<Record*> ProcessorList =
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Records.getAllDerivedDefinitions("Processor");
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sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
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// Begin processor table
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OS << "// Sorted (by key) array of values for CPU subtype.\n"
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<< "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
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// For each processor
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RecordListIter PI(Processors);
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while (Record *R = PI.next()) {
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std::string Name = R->getValueAsString("Name");
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DefListIter FI(R, "Features");
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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// Next processor
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Record *Processor = ProcessorList[i];
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std::string Name = Processor->getValueAsString("Name");
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std::vector<Record*> FeatureList = Processor->getValueAsListDef("Features");
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// Emit as { "cpu", "description", f1 | f2 | ... fn },
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OS << " { "
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<< "\"" << Name << "\", "
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<< "\"Select the " << Name << " processor\", ";
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if (!FI.isMore()) {
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if (FeatureList.empty()) {
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OS << "0";
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} else {
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while (Record *Feature = FI.next()) {
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for (unsigned j = 0, M = FeatureList.size(); j < M;) {
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Record *Feature = FeatureList[j];
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std::string Name = Feature->getName();
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OS << Name;
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if (FI.isMore()) OS << " | ";
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if (++j < M) OS << " | ";
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}
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}
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OS << (PI.isMore() ? " },\n" : " }\n");
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OS << " }";
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// Depending on if more in the list emit comma
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if (++i < N) OS << ",";
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OS << "\n";
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}
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// End processor table
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@ -224,25 +176,26 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) {
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// CollectAllItinClasses - Gathers and enumerates all the itinerary classes.
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// Returns itinerary class count.
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//
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unsigned SubtargetEmitter::CollectAllItinClasses(IntMap &ItinClassesMap) {
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unsigned SubtargetEmitter::CollectAllItinClasses(std::map<std::string, unsigned>
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&ItinClassesMap) {
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// Gather and sort all itinerary classes
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RecordList ICL = Records.getAllDerivedDefinitions("InstrItinClass");
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sort(ICL.begin(), ICL.end(), LessRecord());
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std::vector<Record*> ItinClassList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
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// Track enumeration
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unsigned Index = 0;
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// For each class
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RecordListIter ICI(ICL);
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while (Record *ItinClass = ICI.next()) {
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// For each itinerary class
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unsigned N = ItinClassList.size();
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for (unsigned i = 0; i < N; i++) {
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// Next itinerary class
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Record *ItinClass = ItinClassList[i];
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// Get name of itinerary class
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std::string Name = ItinClass->getName();
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// Assign itinerary class a unique number
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ItinClassesMap[Name] = Index++;
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ItinClassesMap[Name] = i;
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}
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// Return itinerary class count
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return Index;
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return N;
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}
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//
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@ -251,24 +204,31 @@ unsigned SubtargetEmitter::CollectAllItinClasses(IntMap &ItinClassesMap) {
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//
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void SubtargetEmitter::FormItineraryString(Record *ItinData,
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std::string &ItinString,
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unsigned &N) {
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// Set up stages iterator
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DefListIter SLI(ItinData, "Stages");
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// Get stage count
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N = SLI.N;
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unsigned &NStages) {
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// Get states list
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std::vector<Record*> StageList = ItinData->getValueAsListDef("Stages");
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// For each stage
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while (Record *Stage = SLI.next()) {
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unsigned N = NStages = StageList.size();
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for (unsigned i = 0; i < N; i++) {
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// Next stage
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Record *Stage = StageList[i];
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// Form string as ,{ cycles, u1 | u2 | ... | un }
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int Cycles = Stage->getValueAsInt("Cycles");
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ItinString += " ,{ " + itostr(Cycles) + ", ";
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// Get unit list
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std::vector<Record*> UnitList = Stage->getValueAsListDef("Units");
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// For each unit
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DefListIter ULI(Stage, "Units");
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while (Record *Unit = ULI.next()) {
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std::string Name = Unit->getName();
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ItinString += Name;
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if (ULI.isMore())ItinString += " | ";
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for (unsigned j = 0, M = UnitList.size(); j < M;) {
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// Next unit
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Record *Unit = UnitList[j];
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// Add name and bitwise or
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ItinString += Unit->getName();
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if (++j < M) ItinString += " | ";
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}
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// Close off stage
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@ -281,40 +241,48 @@ void SubtargetEmitter::FormItineraryString(Record *ItinData,
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// processors.
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//
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void SubtargetEmitter::EmitStageData(std::ostream &OS,
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unsigned N,
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IntMap &ItinClassesMap,
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ProcessorList &ProcList) {
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unsigned NItinClasses,
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std::map<std::string, unsigned> &ItinClassesMap,
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std::vector<std::vector<InstrItinerary> > &ProcList) {
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// Gather processor iteraries
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RecordList Itins = Records.getAllDerivedDefinitions("ProcessorItineraries");
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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// If just no itinerary then don't bother
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if (Itins.size() < 2) return;
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if (ProcItinList.size() < 2) return;
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// Begin stages table
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OS << "static llvm::InstrStage Stages[] = {\n"
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" { 0, 0 } // No itinerary\n";
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IntMap ItinMap;
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unsigned Index = 1;
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RecordListIter II(Itins);
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while (Record *Itin = II.next()) {
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unsigned ItinEnum = 1;
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std::map<std::string, unsigned> ItinMap;
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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// Next record
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name
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std::string Name = Itin->getName();
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std::string Name = Proc->getName();
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// Skip default
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if (Name == "NoItineraries") continue;
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// Create and expand processor itinerary to cover all itinerary classes
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IntineraryList IL;
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IL.resize(N);
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std::vector<InstrItinerary> ItinList;
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ItinList.resize(NItinClasses);
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// For each itinerary
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DefListIter IDLI(Itin, "IID");
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while (Record *ItinData = IDLI.next()) {
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// Get itinerary data list
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std::vector<Record*> ItinDataList = Proc->getValueAsListDef("IID");
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// For each itinerary data
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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// Next itinerary data
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Record *ItinData = ItinDataList[j];
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// Get string and stage count
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std::string ItinString;
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unsigned M;
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FormItineraryString(ItinData, ItinString, M);
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unsigned NStages;
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FormItineraryString(ItinData, ItinString, NStages);
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// Check to see if it already exists
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unsigned Find = ItinMap[ItinString];
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@ -322,23 +290,23 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS,
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// If new itinerary
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if (Find == 0) {
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// Emit as ,{ cycles, u1 | u2 | ... | un } // index
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OS << ItinString << " // " << Index << "\n";
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ItinMap[ItinString] = Find = Index++;
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OS << ItinString << " // " << ItinEnum << "\n";
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ItinMap[ItinString] = Find = ItinEnum++;
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}
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// Set up itinerary as location and location + stage count
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InstrItinerary Intinerary = { Find, Find + M };
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InstrItinerary Intinerary = { Find, Find + NStages };
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// Locate where to inject into processor itinerary table
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std::string Name = ItinData->getValueAsDef("TheClass")->getName();
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Find = ItinClassesMap[Name];
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// Inject - empty slots will be 0, 0
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IL[Find] = Intinerary;
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ItinList[Find] = Intinerary;
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}
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// Add process itinerary to list
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ProcList.push_back(IL);
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ProcList.push_back(ItinList);
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}
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// End stages table
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@ -349,14 +317,18 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS,
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// EmitProcessData - Generate data for processor itineraries.
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//
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void SubtargetEmitter::EmitProcessData(std::ostream &OS,
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ProcessorList &ProcList) {
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std::vector<std::vector<InstrItinerary> > &ProcList) {
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// Get an iterator for processor itinerary stages
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ProcessorList::iterator PLI = ProcList.begin();
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std::vector<std::vector<InstrItinerary> >::iterator
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ProcListIter = ProcList.begin();
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// For each processor itinerary
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RecordList Itins = Records.getAllDerivedDefinitions("ProcessorItineraries");
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RecordListIter II(Itins);
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while (Record *Itin = II.next()) {
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std::vector<Record*> Itins =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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for (unsigned i = 0, N = Itins.size(); i < N; i++) {
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// Next record
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Record *Itin = Itins[i];
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// Get processor itinerary name
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std::string Name = Itin->getName();
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@ -368,10 +340,10 @@ void SubtargetEmitter::EmitProcessData(std::ostream &OS,
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OS << "static llvm::InstrItinerary " << Name << "[] = {\n";
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// For each itinerary class
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IntineraryList &IL = *PLI++;
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unsigned Index = 0;
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for (IntineraryList::iterator ILI = IL.begin(), E = IL.end(); ILI != E;) {
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InstrItinerary &Intinerary = *ILI++;
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std::vector<InstrItinerary> &ItinList = *ProcListIter++;
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unsigned ItinIndex = 0;
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for (unsigned j = 0, M = ItinList.size(); j < M;) {
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InstrItinerary &Intinerary = ItinList[j];
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// Emit in the form of { first, last } // index
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if (Intinerary.First == 0) {
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@ -380,8 +352,10 @@ void SubtargetEmitter::EmitProcessData(std::ostream &OS,
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OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }";
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}
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if (ILI != E) OS << ",";
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OS << " // " << Index++ << "\n";
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// If more in list add comma
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if (++j < M) OS << ",";
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OS << " // " << (j - 1) << "\n";
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}
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// End processor itinerary table
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@ -393,13 +367,13 @@ void SubtargetEmitter::EmitProcessData(std::ostream &OS,
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// EmitData - Emits all stages and itineries, folding common patterns.
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//
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void SubtargetEmitter::EmitData(std::ostream &OS) {
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IntMap ItinClassesMap;
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ProcessorList ProcList;
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std::map<std::string, unsigned> ItinClassesMap;
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std::vector<std::vector<InstrItinerary> > ProcList;
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// Enumerate all the itinerary classes
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unsigned N = CollectAllItinClasses(ItinClassesMap);
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unsigned NItinClasses = CollectAllItinClasses(ItinClassesMap);
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// Emit the stage data
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EmitStageData(OS, N, ItinClassesMap, ProcList);
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EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList);
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// Emit the processor itinerary data
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EmitProcessData(OS, ProcList);
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}
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@ -409,7 +383,8 @@ void SubtargetEmitter::EmitData(std::ostream &OS) {
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// the subtarget features string.
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//
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void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
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RecordList Features = Records.getAllDerivedDefinitions("SubtargetFeature");
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std::vector<Record*> Features =
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Records.getAllDerivedDefinitions("SubtargetFeature");
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||||
sort(Features.begin(), Features.end(), LessRecord());
|
||||
|
||||
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
|
||||
@ -423,8 +398,9 @@ void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
|
||||
" uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n"
|
||||
" FeatureKV, FeatureKVSize);\n";
|
||||
|
||||
RecordListIter FI(Features);
|
||||
while (Record *R = FI.next()) {
|
||||
for (unsigned i = 0; i < Features.size(); i++) {
|
||||
// Next record
|
||||
Record *R = Features[i];
|
||||
std::string Instance = R->getName();
|
||||
std::string Name = R->getValueAsString("Name");
|
||||
std::string Type = R->getValueAsString("Type");
|
||||
|
@ -23,13 +23,6 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
//
|
||||
// Convenience types.
|
||||
//
|
||||
typedef std::map<std::string, unsigned> IntMap;
|
||||
typedef std::vector<InstrItinerary> IntineraryList;
|
||||
typedef std::vector<IntineraryList> ProcessorList;
|
||||
|
||||
class SubtargetEmitter : public TableGenBackend {
|
||||
|
||||
RecordKeeper &Records;
|
||||
@ -38,12 +31,15 @@ class SubtargetEmitter : public TableGenBackend {
|
||||
void Enumeration(std::ostream &OS, const char *ClassName, bool isBits);
|
||||
void FeatureKeyValues(std::ostream &OS);
|
||||
void CPUKeyValues(std::ostream &OS);
|
||||
unsigned CollectAllItinClasses(IntMap &ItinClassesMap);
|
||||
unsigned CollectAllItinClasses(std::map<std::string, unsigned>
|
||||
&ItinClassesMap);
|
||||
void FormItineraryString(Record *ItinData, std::string &ItinString,
|
||||
unsigned &N);
|
||||
void EmitStageData(std::ostream &OS, unsigned N,
|
||||
IntMap &ItinClassesMap, ProcessorList &ProcList);
|
||||
void EmitProcessData(std::ostream &OS, ProcessorList &ProcList);
|
||||
unsigned &NStages);
|
||||
void EmitStageData(std::ostream &OS, unsigned NItinClasses,
|
||||
std::map<std::string, unsigned> &ItinClassesMap,
|
||||
std::vector<std::vector<InstrItinerary> > &ProcList);
|
||||
void EmitProcessData(std::ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> > &ProcList);
|
||||
void EmitData(std::ostream &OS);
|
||||
void ParseFeaturesFunction(std::ostream &OS);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user