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Emit inc / dec of registers as one byte instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29110 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1095,9 +1095,9 @@ let isTwoAddress = 0 in {
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def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
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def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
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[(set GR8:$dst, (add GR8:$src, 1))]>;
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[(set GR8:$dst, (add GR8:$src, 1))]>;
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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def INC16r : I<0xFF, MRM0r, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
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def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
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[(set GR16:$dst, (add GR16:$src, 1))]>, OpSize;
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[(set GR16:$dst, (add GR16:$src, 1))]>, OpSize;
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def INC32r : I<0xFF, MRM0r, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
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def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
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[(set GR32:$dst, (add GR32:$src, 1))]>;
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[(set GR32:$dst, (add GR32:$src, 1))]>;
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}
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}
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let isTwoAddress = 0 in {
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let isTwoAddress = 0 in {
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@ -1112,9 +1112,9 @@ let isTwoAddress = 0 in {
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def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
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def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
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[(set GR8:$dst, (add GR8:$src, -1))]>;
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[(set GR8:$dst, (add GR8:$src, -1))]>;
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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def DEC16r : I<0xFF, MRM1r, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
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def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
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[(set GR16:$dst, (add GR16:$src, -1))]>, OpSize;
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[(set GR16:$dst, (add GR16:$src, -1))]>, OpSize;
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def DEC32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
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def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
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[(set GR32:$dst, (add GR32:$src, -1))]>;
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[(set GR32:$dst, (add GR32:$src, -1))]>;
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}
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}
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