mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add all that branch mangling niftiness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31313 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
b191e0ab51
commit
f81173f70e
@ -32,6 +32,7 @@ namespace llvm {
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FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
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MachineCodeEmitter &MCE);
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FunctionPass *createAlphaLLRPPass(AlphaTargetMachine &tm);
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FunctionPass *createAlphaBranchSelectionPass();
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} // end namespace llvm;
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63
lib/Target/Alpha/AlphaBranchSelector.cpp
Normal file
63
lib/Target/Alpha/AlphaBranchSelector.cpp
Normal file
@ -0,0 +1,63 @@
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//===-- AlphaBranchSelector.cpp - Convert Pseudo branchs ----------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Replace Pseudo COND_BRANCH_* with their appropriate real branch
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// Simplified version of the PPC Branch Selector
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetAsmInfo.h"
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using namespace llvm;
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namespace {
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struct VISIBILITY_HIDDEN AlphaBSel : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "Alpha Branch Selection";
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}
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};
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}
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/// createAlphaBranchSelectionPass - returns an instance of the Branch Selection
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/// Pass
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///
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FunctionPass *llvm::createAlphaBranchSelectionPass() {
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return new AlphaBSel();
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}
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bool AlphaBSel::runOnMachineFunction(MachineFunction &Fn) {
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock *MBB = MFI;
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for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
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MBBI != EE; ++MBBI) {
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if (MBBI->getOpcode() == Alpha::COND_BRANCH_I ||
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MBBI->getOpcode() == Alpha::COND_BRANCH_F) {
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// condbranch operands:
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// 0. bc opcode
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// 1. reg
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// 2. target MBB
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MBBI->setOpcode(MBBI->getOperand(0).getImm());
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}
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}
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}
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return true;
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}
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@ -164,6 +164,8 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AlphaISD::CALL: return "Alpha::CALL";
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case AlphaISD::DivCall: return "Alpha::DivCall";
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case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
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case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
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case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
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}
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}
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@ -46,7 +46,15 @@ namespace llvm {
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DivCall,
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/// return flag operand
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RET_FLAG
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RET_FLAG,
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/// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction.
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/// *PRC is the input register to compare to zero,
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/// OPC is the branch opcode to use (e.g. Alpha::BEQ),
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/// DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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COND_BRANCH_I, COND_BRANCH_F
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};
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}
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@ -22,6 +22,7 @@ def s14imm : Operand<i64>;
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def s16imm : Operand<i64>;
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def s21imm : Operand<i64>;
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def s64imm : Operand<i64>;
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def u64imm : Operand<i64>;
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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@ -92,6 +93,20 @@ class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> patt
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//3.3.2
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def target : Operand<OtherVT> {}
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
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class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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let OperandList = OL;
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bits<64> Opc; //dummy
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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}
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let isBranch = 1, isTerminator = 1 in
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class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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@ -103,31 +118,6 @@ class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass it
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class BForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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let Pattern = pattern;
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let OperandList = (ops GPRC:$RA, target:$DISP);
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class FBForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
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: InstAlpha<opcode, asmstr, itin> {
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let Pattern = pattern;
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let OperandList = (ops F8RC:$RA, target:$DISP);
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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//3.3.3
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class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
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@ -83,10 +83,170 @@ AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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return 0;
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}
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static bool isAlphaIntCondCode(unsigned Opcode) {
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switch (Opcode) {
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case Alpha::BEQ:
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case Alpha::BNE:
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case Alpha::BGE:
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case Alpha::BGT:
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case Alpha::BLE:
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case Alpha::BLT:
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case Alpha::BLBC:
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case Alpha::BLBS:
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return true;
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default:
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return false;
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}
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}
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void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond)const{
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Alpha branch conditions have two components!");
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
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else // Conditional branch
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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return;
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}
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// Two-way Conditional Branch.
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if (isAlphaIntCondCode(Cond[0].getImm()))
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BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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else
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BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB);
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}
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static unsigned AlphaRevCondCode(unsigned Opcode) {
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switch (Opcode) {
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case Alpha::BEQ: return Alpha::BNE;
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case Alpha::BNE: return Alpha::BEQ;
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case Alpha::BGE: return Alpha::BLT;
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case Alpha::BGT: return Alpha::BLE;
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case Alpha::BLE: return Alpha::BGT;
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case Alpha::BLT: return Alpha::BGE;
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case Alpha::BLBC: return Alpha::BLBS;
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case Alpha::BLBS: return Alpha::BLBC;
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case Alpha::FBEQ: return Alpha::FBNE;
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case Alpha::FBNE: return Alpha::FBEQ;
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case Alpha::FBGE: return Alpha::FBLT;
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case Alpha::FBGT: return Alpha::FBLE;
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case Alpha::FBLE: return Alpha::FBGT;
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case Alpha::FBLT: return Alpha::FBGE;
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default:
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assert(0 && "Unknown opcode");
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}
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}
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// Branch analysis.
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bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
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if (LastInst->getOpcode() == Alpha::BR) {
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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} else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
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LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(2).getMachineBasicBlock();
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Cond.push_back(LastInst->getOperand(0));
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Cond.push_back(LastInst->getOperand(1));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isTerminatorInstr((--I)->getOpcode()))
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return true;
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// If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
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if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
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SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
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LastInst->getOpcode() == Alpha::BR) {
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TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
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Cond.push_back(SecondLastInst->getOperand(0));
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != Alpha::BR &&
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I->getOpcode() != Alpha::COND_BRANCH_I &&
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I->getOpcode() != Alpha::COND_BRANCH_F)
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return;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != Alpha::COND_BRANCH_I &&
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I->getOpcode() != Alpha::COND_BRANCH_F)
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return;
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// Remove the branch.
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I->eraseFromParent();
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}
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void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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}
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bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case Alpha::BR: // Uncond branch.
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case Alpha::JMP: // Indirect branch.
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return true;
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default: return false;
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}
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}
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bool AlphaInstrInfo::
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ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
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Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
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return false;
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}
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@ -42,6 +42,14 @@ public:
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virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const;
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void RemoveBranch(MachineBasicBlock &MBB) const;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
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};
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}
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@ -847,120 +847,173 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
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/////////////////////////////////////////////////////////
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//Branching
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/////////////////////////////////////////////////////////
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class br_icc<bits<6> opc, string asmstr>
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: BFormN<opc, (ops u64imm:$opc, GPRC:$R, target:$dst),
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!strconcat(asmstr, " $R,$dst"), s_icbr>;
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class br_fcc<bits<6> opc, string asmstr>
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: BFormN<opc, (ops u64imm:$opc, F8RC:$R, target:$dst),
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!strconcat(asmstr, " $R,$dst"), s_fbr>;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
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let Ra = 31 in
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def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;
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def COND_BRANCH_I : BFormN<0, (ops u64imm:$opc, GPRC:$R, target:$dst),
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"{:comment} COND_BRANCH imm:$opc, GPRC:$R, bb:$dst",
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s_icbr>;
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def COND_BRANCH_F : BFormN<0, (ops u64imm:$opc, F8RC:$R, target:$dst),
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"{:comment} COND_BRANCH imm:$opc, F8RC:$R, bb:$dst",
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s_fbr>;
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP",
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[(brcond (seteq GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BGE : BForm<0x3E, "bge $RA,$DISP",
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[(brcond (setge GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BGT : BForm<0x3F, "bgt $RA,$DISP",
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[(brcond (setgt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BLBC : BForm<0x38, "blbc $RA,$DISP", [], s_icbr>; //TODO: Low bit clear
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def BLBS : BForm<0x3C, "blbs $RA,$DISP",
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[(brcond (and GPRC:$RA, 1), bb:$DISP)], s_icbr>;
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def BLE : BForm<0x3B, "ble $RA,$DISP",
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[(brcond (setle GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BLT : BForm<0x3A, "blt $RA,$DISP",
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[(brcond (setlt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BNE : BForm<0x3D, "bne $RA,$DISP",
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[(brcond (setne GPRC:$RA, 0), bb:$DISP)], s_icbr>;
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def BEQ : br_icc<0x39, "beq">;
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def BGE : br_icc<0x3E, "bge">;
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def BGT : br_icc<0x3F, "bgt">;
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def BLBC : br_icc<0x38, "blbc">;
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def BLBS : br_icc<0x3C, "blbs">;
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def BLE : br_icc<0x3B, "ble">;
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def BLT : br_icc<0x3A, "blt">;
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def BNE : br_icc<0x3D, "bne">;
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//Branches, float
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def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
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[(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
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def FBGE : FBForm<0x36, "fbge $RA,$DISP",
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[(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
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def FBGT : FBForm<0x37, "fbgt $RA,$DISP",
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[(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
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def FBLE : FBForm<0x33, "fble $RA,$DISP",
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[(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
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def FBLT : FBForm<0x32, "fblt $RA,$DISP",
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[(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
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def FBNE : FBForm<0x35, "fbne $RA,$DISP",
|
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[(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
|
||||
def FBEQ : br_fcc<0x31, "fbeq">;
|
||||
def FBGE : br_fcc<0x36, "fbge">;
|
||||
def FBGT : br_fcc<0x37, "fbgt">;
|
||||
def FBLE : br_fcc<0x33, "fble">;
|
||||
def FBLT : br_fcc<0x32, "fblt">;
|
||||
def FBNE : br_fcc<0x36, "fbne">;
|
||||
}
|
||||
|
||||
def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>;
|
||||
//An ugly trick to get the opcode as an imm I can use
|
||||
def immBRCond : SDNodeXForm<imm, [{
|
||||
switch((uint64_t)N->getValue()) {
|
||||
case 0: return getI64Imm(Alpha::BEQ);
|
||||
case 1: return getI64Imm(Alpha::BNE);
|
||||
case 2: return getI64Imm(Alpha::BGE);
|
||||
case 3: return getI64Imm(Alpha::BGT);
|
||||
case 4: return getI64Imm(Alpha::BLE);
|
||||
case 5: return getI64Imm(Alpha::BLT);
|
||||
case 6: return getI64Imm(Alpha::BLBS);
|
||||
case 7: return getI64Imm(Alpha::BLBC);
|
||||
case 20: return getI64Imm(Alpha::FBEQ);
|
||||
case 21: return getI64Imm(Alpha::FBNE);
|
||||
case 22: return getI64Imm(Alpha::FBGE);
|
||||
case 23: return getI64Imm(Alpha::FBGT);
|
||||
case 24: return getI64Imm(Alpha::FBLE);
|
||||
case 25: return getI64Imm(Alpha::FBLT);
|
||||
default: assert(0 && "Unknown branch type");
|
||||
}
|
||||
}]>;
|
||||
|
||||
//Int cond patterns
|
||||
def : Pat<(brcond (seteq GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 0), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setge GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 2), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setgt GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 3), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (and GPRC:$RA, 1), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 6), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setle GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 4), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setlt GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 5), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setne GPRC:$RA, 0), bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 1), GPRC:$RA, bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond GPRC:$RA, bb:$DISP),
|
||||
(COND_BRANCH_I (immBRCond 1), GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setne GPRC:$RA, GPRC:$RB), bb:$DISP),
|
||||
(BEQ (CMPEQ GPRC:$RA, GPRC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_I (immBRCond 0), (CMPEQ GPRC:$RA, GPRC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setne GPRC:$RA, immUExt8:$L), bb:$DISP),
|
||||
(BEQ (CMPEQi GPRC:$RA, immUExt8:$L), bb:$DISP)>;
|
||||
(COND_BRANCH_I (immBRCond 0), (CMPEQi GPRC:$RA, immUExt8:$L), bb:$DISP)>;
|
||||
|
||||
//FP cond patterns
|
||||
def : Pat<(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 20), F8RC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setne F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 21), F8RC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setge F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 22), F8RC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 23), F8RC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setle F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 24), F8RC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(COND_BRANCH_F (immBRCond 25), F8RC:$RA, bb:$DISP)>;
|
||||
|
||||
|
||||
def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setoeq F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setueq F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setolt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setult F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setole F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setule F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setogt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setugt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setoge F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setuge F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setone F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setune F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
|
||||
|
||||
def : Pat<(brcond (setoeq F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBEQ F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 20), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setueq F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBEQ F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 20), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setoge F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBGE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 22), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setuge F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBGE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 22), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setogt F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBGT F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 23), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setugt F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBGT F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 23), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setole F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBLE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 24), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setule F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBLE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 24), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setolt F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBLT F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 25), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setult F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBLT F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 25), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
def : Pat<(brcond (setone F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBNE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), F8RC:$RA,bb:$DISP)>;
|
||||
def : Pat<(brcond (setune F8RC:$RA, immFPZ), bb:$DISP),
|
||||
(FBNE F8RC:$RA,bb:$DISP)>;
|
||||
(COND_BRANCH_F (immBRCond 21), F8RC:$RA,bb:$DISP)>;
|
||||
|
||||
//End Branches
|
||||
|
||||
|
||||
@ -74,7 +74,7 @@ bool AlphaTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
|
||||
}
|
||||
bool AlphaTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
|
||||
// Must run branch selection immediately preceding the asm printer
|
||||
//PM.add(createAlphaBranchSelectionPass());
|
||||
PM.add(createAlphaBranchSelectionPass());
|
||||
return false;
|
||||
}
|
||||
bool AlphaTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user