From f819a4999aedd00368c850c1707e7ed0d59b4ace Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Thu, 9 Nov 2006 13:58:55 +0000 Subject: [PATCH] implement load effective address similar to the alpha backend remove lea_addri and the now unused memri addressing mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 27 ------------------ lib/Target/ARM/ARMISelDAGToDAG.cpp | 45 ++++++++---------------------- lib/Target/ARM/ARMInstrInfo.td | 17 ----------- lib/Target/ARM/ARMRegisterInfo.cpp | 8 +++--- 4 files changed, 15 insertions(+), 82 deletions(-) diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 367b3da4396..51a0f883d2d 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -78,33 +78,6 @@ namespace { void printAddrMode1(const MachineInstr *MI, int opNum); void printAddrMode2(const MachineInstr *MI, int opNum); void printAddrMode5(const MachineInstr *MI, int opNum); - - void printMemRegImm(const MachineInstr *MI, int opNum, - const char *Modifier = NULL) { - const MachineOperand &MO1 = MI->getOperand(opNum); - const MachineOperand &MO2 = MI->getOperand(opNum + 1); - assert(MO1.isImmediate()); - bool arith = false; - if (Modifier != NULL) { - assert(strcmp(Modifier, "arith") == 0); - arith = true; - } - - if (MO2.isConstantPoolIndex()) { - printOperand(MI, opNum + 1); - } else if (MO2.isRegister()) { - if(!arith) - O << '['; - printOperand(MI, opNum + 1); - O << ", "; - printOperand(MI, opNum); - if(!arith) - O << ']'; - } else { - assert(0 && "Invalid Operand Type"); - } - } - void printOperand(const MachineInstr *MI, int opNum); void printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier = 0); diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index d49427dfa76..a7e4703a665 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -751,8 +751,6 @@ public: SDNode *Select(SDOperand Op); virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); - bool SelectAddrRegImm(SDOperand Op, SDOperand N, SDOperand &Offset, - SDOperand &Base); bool SelectAddrMode1(SDOperand Op, SDOperand N, SDOperand &Arg, SDOperand &Shift, SDOperand &ShiftType); bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Arg, @@ -895,37 +893,6 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, return true; } -//register plus/minus 12 bit offset -bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand Op, - SDOperand N, SDOperand &Offset, - SDOperand &Base) { - if (FrameIndexSDNode *FIN = dyn_cast(N)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); - return true; - } - if (N.getOpcode() == ISD::ADD) { - short imm = 0; - if (isInt12Immediate(N.getOperand(1), imm)) { - Offset = CurDAG->getTargetConstant(imm, MVT::i32); - if (FrameIndexSDNode *FI = dyn_cast(N.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - } else { - Base = N.getOperand(0); - } - return true; // [r+i] - } - } - - Offset = CurDAG->getTargetConstant(0, MVT::i32); - if (FrameIndexSDNode *FI = dyn_cast(N)) { - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - } - else - Base = N; - return true; //any address fits in a register -} - SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { SDNode *N = Op.Val; @@ -933,8 +900,18 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { default: return SelectCode(Op); break; + case ISD::FrameIndex: { + int FI = cast(N)->getIndex(); + SDOperand Ops[] = {CurDAG->getTargetFrameIndex(FI, MVT::i32), + CurDAG->getTargetConstant(0, MVT::i32), + CurDAG->getTargetConstant(0, MVT::i32), + CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32)}; + + return CurDAG->SelectNodeTo(N, ARM::ADD, MVT::i32, Ops, + sizeof(Ops)/sizeof(SDOperand)); + break; + } } - return NULL; } } // end anonymous namespace diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 6945540da07..f7043303441 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -28,11 +28,6 @@ def op_addr_mode5 : Operand { let MIOperandInfo = (ops ptr_rc, i32imm); } -def memri : Operand { - let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops i32imm, ptr_rc); -} - // Define ARM specific addressing mode. //Addressing Mode 1: data processing operands def addr_mode1 : ComplexPattern; //Addressing Mode 5: VFP load/store def addr_mode5 : ComplexPattern; -//register plus/minus 12 bit offset -def iaddr : ComplexPattern; -//register plus scaled register -//def raddr : ComplexPattern; - //===----------------------------------------------------------------------===// // Instruction Class Templates //===----------------------------------------------------------------------===// @@ -203,13 +193,6 @@ def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src), def ADD : Addr1BinOp<"add", add>; def ADCS : Addr1BinOp<"adcs", adde>; def ADDS : Addr1BinOp<"adds", addc>; - -// "LEA" forms of add -def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr), - "add $dst, ${addr:arith}", - [(set IntRegs:$dst, iaddr:$addr)]>; - - def SUB : Addr1BinOp<"sub", sub>; def SBCS : Addr1BinOp<"sbcs", sube>; def SUBS : Addr1BinOp<"subs", subc>; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 4a8fa1ee4d1..3b5ed6a0fad 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -129,11 +129,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MachineFunction &MF = *MBB.getParent(); assert (MI.getOpcode() == ARM::LDR || - MI.getOpcode() == ARM::STR || - MI.getOpcode() == ARM::lea_addri); + MI.getOpcode() == ARM::STR || + MI.getOpcode() == ARM::ADD); - unsigned FrameIdx = MI.getOpcode() == ARM::lea_addri ? 2 : 1; - unsigned OffIdx = MI.getOpcode() == ARM::lea_addri ? 1 : 2; + unsigned FrameIdx = 1; + unsigned OffIdx = 2; int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();