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[X86][fast-isel] Fix select lowering.

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The condition in selects is supposed to be i1.
Make sure we are just reading the less significant bit
of the 8 bits width value to match this constraint.

<rdar://problem/15651765>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2013-12-19 18:32:04 +00:00
parent 3793977e90
commit f847657767
2 changed files with 23 additions and 2 deletions
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9
lib/Target/X86/X86FastISel.cpp
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@ -1508,8 +1508,13 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) {
unsigned Op2Reg = getRegForValue(I->getOperand(2));
if (Op2Reg == 0) return false;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
.addReg(Op0Reg).addReg(Op0Reg);
// Selects operate on i1, however, Op0Reg is 8 bits width and may contain
// garbage. Indeed, only the less significant bit is supposed to be accurate.
// If we read more than the lsb, we may see non-zero values whereas lsb
// is zero. Therefore, we have to truncate Op0Reg to i1 for the select.
// This is acheived by performing TEST against 1.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
.addReg(Op0Reg).addImm(1);
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
.addReg(Op1Reg).addReg(Op2Reg);

16
test/CodeGen/X86/fast-isel-select.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc -mtriple x86_64-apple-darwin -O0 -o - < %s | FileCheck %s
; Make sure we only use the less significant bit of the value that feeds the
; select. Otherwise, we may account for a non-zero value whereas the
; lsb is zero.
; <rdar://problem/15651765>
; CHECK-LABEL: fastisel_select:
; CHECK: subb {{%[a-z0-9]+}}, [[RES:%[a-z0-9]+]]
; CHECK: testb $1, [[RES]]
; CHECK: cmovel
define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) {
%shuffleInternal15257_8932 = sub i1 %exchSub2211_, %trunc_8766
%counter_diff1345 = select i1 %shuffleInternal15257_8932, i32 1204476887, i32 0
ret i32 %counter_diff1345
}