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Revert r79127. It was causing compilation errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -637,13 +637,13 @@ public:
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unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
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/// This function returns true if the target allows unaligned memory accesses.
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/// of the specified type. This is used, for example, in situations where an
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/// array copy/move/set is converted to a sequence of store operations. It's
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/// use helps to ensure that such replacements don't generate code that causes
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/// an alignment error (trap) on the target machine.
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/// This is used, for example, in situations where an array copy/move/set is
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/// converted to a sequence of store operations. It's use helps to ensure that
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/// such replacements don't generate code that causes an alignment error
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/// (trap) on the target machine.
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/// @brief Determine if the target supports unaligned memory accesses.
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
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return false;
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bool allowsUnalignedMemoryAccesses() const {
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return allowUnalignedMemoryAccesses;
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}
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/// This function returns true if the target would benefit from code placement
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@ -1757,6 +1757,12 @@ protected:
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/// @brief Specify maximum bytes of store instructions per memmove call.
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unsigned maxStoresPerMemmove;
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/// This field specifies whether the target machine permits unaligned memory
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/// accesses. This is used, for example, to determine the size of store
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/// operations when copying small arrays and other similar tasks.
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/// @brief Indicate whether the target permits unaligned memory accesses.
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bool allowUnalignedMemoryAccesses;
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/// This field specifies whether the target can benefit from code placement
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/// optimization.
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bool benefitFromCodePlacementOpt;
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@ -3121,27 +3121,6 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return SDValue();
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}
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bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
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if (!Subtarget->hasV6Ops())
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// Pre-v6 does not support unaligned mem access.
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return false;
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else if (!Subtarget->hasV6Ops()) {
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// v6 may or may not support unaligned mem access.
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if (!Subtarget->isTargetDarwin())
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return false;
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}
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switch (VT.getSimpleVT().SimpleTy) {
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default:
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return false;
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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return true;
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// FIXME: VLD1 etc with standard alignment is legal.
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}
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}
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static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
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if (V < 0)
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return false;
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@ -166,11 +166,6 @@ namespace llvm {
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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/// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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@ -198,8 +193,6 @@ namespace llvm {
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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@ -957,6 +957,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
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maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
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maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
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allowUnalignedMemoryAccesses = true; // x86 supports it!
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setPrefLoopAlignment(16);
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benefitFromCodePlacementOpt = true;
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}
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@ -389,16 +389,11 @@ namespace llvm {
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
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/// determining it.
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
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virtual
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EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
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bool isSrcConst, bool isSrcStr,
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SelectionDAG &DAG) const;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
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return true;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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@ -367,10 +367,9 @@ SDValue XCoreTargetLowering::
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LowerLOAD(SDValue Op, SelectionDAG &DAG)
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{
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LoadSDNode *LD = cast<LoadSDNode>(Op);
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assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
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"Unexpected extension type");
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assert(LD->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension type");
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assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
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if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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if (allowsUnalignedMemoryAccesses()) {
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return SDValue();
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}
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unsigned ABIAlignment = getTargetData()->
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@ -466,7 +465,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG)
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StoreSDNode *ST = cast<StoreSDNode>(Op);
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assert(!ST->isTruncatingStore() && "Unexpected store type");
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assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
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if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
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if (allowsUnalignedMemoryAccesses()) {
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return SDValue();
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}
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unsigned ABIAlignment = getTargetData()->
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@ -1049,8 +1048,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::STORE: {
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// Replace unaligned store of unaligned load with memmove.
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StoreSDNode *ST = cast<StoreSDNode>(N);
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if (!DCI.isBeforeLegalize() ||
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allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
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if (!DCI.isBeforeLegalize() || allowsUnalignedMemoryAccesses() ||
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ST->isVolatile() || ST->isIndexed()) {
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break;
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}
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@ -1,31 +1,16 @@
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; RUN: llvm-as < %s | llc -march=arm | FileCheck %s -check-prefix=GENERIC
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; RUN: llvm-as < %s | llc -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6
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; RUN: llvm-as < %s | llc -march=arm -mattr=+v7a | FileCheck %s -check-prefix=V7
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; RUN: llvm-as < %s | \
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; RUN: llc -march=arm -o %t -f
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; RUN: grep ldrb %t | count 4
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; RUN: grep strb %t | count 4
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; rdar://7113725
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define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
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%struct.p = type <{ i8, i32 }>
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@t = global %struct.p <{ i8 1, i32 10 }> ; <%struct.p*> [#uses=1]
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@u = weak global %struct.p zeroinitializer ; <%struct.p*> [#uses=1]
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define i32 @main() {
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entry:
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; GENERIC: t:
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; GENERIC: ldrb r2
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; GENERIC: ldrb r3
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; GENERIC: ldrb r12
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; GENERIC: ldrb r1
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; GENERIC: strb r1
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; GENERIC: strb r12
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; GENERIC: strb r3
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; GENERIC: strb r2
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; DARWIN_V6: t:
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; DARWIN_V6: ldr r1
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; DARWIN_V6: str r1
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; V7: t:
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; V7: ldr r1
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; V7: str r1
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%__src1.i = bitcast i8* %b to i32* ; <i32*> [#uses=1]
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%__dest2.i = bitcast i8* %a to i32* ; <i32*> [#uses=1]
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%tmp.i = load i32* %__src1.i, align 1 ; <i32> [#uses=1]
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store i32 %tmp.i, i32* %__dest2.i, align 1
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ret void
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%tmp3 = load i32* getelementptr (%struct.p* @t, i32 0, i32 1), align 1 ; <i32> [#uses=2]
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store i32 %tmp3, i32* getelementptr (%struct.p* @u, i32 0, i32 1), align 1
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ret i32 %tmp3
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}
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