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Suppress emmission of empty subreg/superreg/alias sets.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-05-26 21:35:55 +00:00
parent 77051f58e9
commit f86a619314
1 changed files with 9 additions and 3 deletions
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12
utils/TableGen/RegisterInfoEmitter.cpp
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@ -719,6 +719,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// to memory. // to memory.
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
if (I->second.empty())
continue;
OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
for (std::set<Record*>::iterator ASI = I->second.begin(), for (std::set<Record*>::iterator ASI = I->second.begin(),
E = I->second.end(); ASI != E; ++ASI) E = I->second.end(); ASI != E; ++ASI)
@ -735,6 +737,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// sub-registers list to memory. // sub-registers list to memory.
for (std::map<Record*, std::set<Record*>, LessRecord>::iterator for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
if (I->second.empty())
continue;
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
std::vector<Record*> SubRegsVector; std::vector<Record*> SubRegsVector;
for (std::set<Record*>::iterator ASI = I->second.begin(), for (std::set<Record*>::iterator ASI = I->second.begin(),
@ -756,6 +760,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// super-registers list to memory. // super-registers list to memory.
for (std::map<Record*, std::set<Record*>, LessRecord >::iterator for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
if (I->second.empty())
continue;
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
std::vector<Record*> SuperRegsVector; std::vector<Record*> SuperRegsVector;
@ -778,15 +784,15 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
const CodeGenRegister &Reg = Regs[i]; const CodeGenRegister &Reg = Regs[i];
OS << " { \""; OS << " { \"";
OS << Reg.getName() << "\",\t"; OS << Reg.getName() << "\",\t";
if (RegisterAliases.count(Reg.TheDef)) if (!RegisterAliases[Reg.TheDef].empty())
OS << Reg.getName() << "_AliasSet,\t"; OS << Reg.getName() << "_AliasSet,\t";
else else
OS << "Empty_AliasSet,\t"; OS << "Empty_AliasSet,\t";
if (RegisterSubRegs.count(Reg.TheDef)) if (!RegisterSubRegs[Reg.TheDef].empty())
OS << Reg.getName() << "_SubRegsSet,\t"; OS << Reg.getName() << "_SubRegsSet,\t";
else else
OS << "Empty_SubRegsSet,\t"; OS << "Empty_SubRegsSet,\t";
if (RegisterSuperRegs.count(Reg.TheDef)) if (!RegisterSuperRegs[Reg.TheDef].empty())
OS << Reg.getName() << "_SuperRegsSet },\n"; OS << Reg.getName() << "_SuperRegsSet },\n";
else else
OS << "Empty_SuperRegsSet },\n"; OS << "Empty_SuperRegsSet },\n";