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R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies

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This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-11-26 18:18:28 +00:00
parent 47539e066c
commit f87cce1540
1 changed files with 3 additions and 3 deletions
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6
lib/Target/R600/SILowerI1Copies.cpp
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@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
if (MI.getOpcode() == AMDGPU::V_AND_I1) {
I1Defs.push_back(MI.getOperand(0).getReg());
MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64));
continue;
}
if (MI.getOpcode() == AMDGPU::V_OR_I1) {
I1Defs.push_back(MI.getOperand(0).getReg());
MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64));
continue;
}
if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
I1Defs.push_back(MI.getOperand(0).getReg());
MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64));
continue;
}