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Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -344,7 +344,12 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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if (I == Instructions.end())
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throw "Could not find 'SUBREG_TO_REG' instruction!";
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const CodeGenInstruction *SUBREG_TO_REG = &I->second;
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I = getInstructions().find("COPY_TO_SUBCLASS");
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if (I == Instructions.end())
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throw "Could not find 'COPY_TO_SUBCLASS' instruction!";
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const CodeGenInstruction *COPY_TO_SUBCLASS = &I->second;
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// Print out the rest of the instructions now.
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(INLINEASM);
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@@ -356,6 +361,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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NumberedInstructions.push_back(INSERT_SUBREG);
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NumberedInstructions.push_back(IMPLICIT_DEF);
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NumberedInstructions.push_back(SUBREG_TO_REG);
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NumberedInstructions.push_back(COPY_TO_SUBCLASS);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI &&
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&II->second != INLINEASM &&
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@@ -366,7 +372,8 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&II->second != EXTRACT_SUBREG &&
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&II->second != INSERT_SUBREG &&
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&II->second != IMPLICIT_DEF &&
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&II->second != SUBREG_TO_REG)
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&II->second != SUBREG_TO_REG &&
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&II->second != COPY_TO_SUBCLASS)
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NumberedInstructions.push_back(&II->second);
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}
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