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ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
abf4b382a6
commit
f8da5f5dfa
@ -988,11 +988,36 @@ class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
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}
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// Misc Arithmetic instructions.
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class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
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opc, asm, "", pattern> {
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bits<4> Rd;
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bits<4> Rm;
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let Inst{27-20} = opcod;
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let Inst{19-16} = 0b1111;
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let Inst{15-12} = Rd;
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let Inst{11-8} = 0b1111;
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let Inst{7-4} = opc7_4;
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let Inst{3-0} = Rm;
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}
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// PKH instructions
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class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
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opc, asm, "", pattern> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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bits<8> sh;
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let Inst{27-20} = opcod;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-7} = sh{7-3};
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let Inst{6} = tb;
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let Inst{5-4} = 0b01;
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let Inst{3-0} = Rm;
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}
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//===----------------------------------------------------------------------===//
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@ -2557,55 +2557,35 @@ defm SMUS : AI_sdml<1, "smus">;
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// Misc. Arithmetic Instructions.
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//
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def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
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"clz", "\t$dst, $src",
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[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
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let Inst{7-4} = 0b0001;
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let Inst{11-8} = 0b1111;
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let Inst{19-16} = 0b1111;
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}
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def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "clz", "\t$Rd, $Rm",
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[(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
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def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
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"rbit", "\t$dst, $src",
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[(set GPR:$dst, (ARMrbit GPR:$src))]>,
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Requires<[IsARM, HasV6T2]> {
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let Inst{7-4} = 0b0011;
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let Inst{11-8} = 0b1111;
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let Inst{19-16} = 0b1111;
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}
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def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rbit", "\t$Rd, $Rm",
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[(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
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Requires<[IsARM, HasV6T2]>;
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def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
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"rev", "\t$dst, $src",
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[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
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let Inst{7-4} = 0b0011;
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let Inst{11-8} = 0b1111;
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let Inst{19-16} = 0b1111;
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}
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def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rev", "\t$Rd, $Rm",
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[(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
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def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
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"rev16", "\t$dst, $src",
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[(set GPR:$dst,
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(or (and (srl GPR:$src, (i32 8)), 0xFF),
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(or (and (shl GPR:$src, (i32 8)), 0xFF00),
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(or (and (srl GPR:$src, (i32 8)), 0xFF0000),
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(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{7-4} = 0b1011;
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let Inst{11-8} = 0b1111;
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let Inst{19-16} = 0b1111;
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}
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def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rev16", "\t$Rd, $Rm",
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[(set GPR:$Rd,
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(or (and (srl GPR:$Rm, (i32 8)), 0xFF),
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(or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
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(or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsARM, HasV6]>;
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def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
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"revsh", "\t$dst, $src",
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[(set GPR:$dst,
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def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "revsh", "\t$Rd, $Rm",
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[(set GPR:$Rd,
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(sext_inreg
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(or (srl (and GPR:$src, 0xFF00), (i32 8)),
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(shl GPR:$src, (i32 8))), i16))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{7-4} = 0b1011;
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let Inst{11-8} = 0b1111;
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let Inst{19-16} = 0b1111;
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}
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(or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
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(shl GPR:$Rm, (i32 8))), i16))]>,
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Requires<[IsARM, HasV6]>;
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def lsl_shift_imm : SDNodeXForm<imm, [{
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unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
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@ -2616,21 +2596,19 @@ def lsl_amt : PatLeaf<(i32 imm), [{
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return (N->getZExtValue() < 32);
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}], lsl_shift_imm>;
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def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
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(ins GPR:$src1, GPR:$src2, shift_imm:$sh),
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IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
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[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
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(and (shl GPR:$src2, lsl_amt:$sh),
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0xFFFF0000)))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{6-4} = 0b001;
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}
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def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
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IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
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[(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
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(and (shl GPR:$Rm, lsl_amt:$sh),
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0xFFFF0000)))]>,
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Requires<[IsARM, HasV6]>;
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// Alternate cases for PKHBT where identities eliminate some nodes.
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def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
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(PKHBT GPR:$src1, GPR:$src2, 0)>;
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def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$sh)),
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(PKHBT GPR:$src1, GPR:$src2, (lsl_shift_imm imm16_31:$sh))>;
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def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
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(PKHBT GPR:$Rn, GPR:$Rm, 0)>;
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def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
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(PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
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def asr_shift_imm : SDNodeXForm<imm, [{
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unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
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@ -2643,15 +2621,13 @@ def asr_amt : PatLeaf<(i32 imm), [{
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// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
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// will match the pattern below.
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def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
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(ins GPR:$src1, GPR:$src2, shift_imm:$sh),
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IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh",
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[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
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(and (sra GPR:$src2, asr_amt:$sh),
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0xFFFF)))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{6-4} = 0b101;
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}
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def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
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IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
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[(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
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(and (sra GPR:$Rm, asr_amt:$sh),
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0xFFFF)))]>,
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Requires<[IsARM, HasV6]>;
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// Alternate cases for PKHTB where identities eliminate some nodes. Note that
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// a shift amount of 0 is *not legal* here, it is PKHBT instead.
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@ -7,6 +7,9 @@
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; compiler never generates, so we need the integrated assembler to be
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; able to test those at all.
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declare void @llvm.trap() nounwind
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declare i32 @llvm.ctlz.i32(i32)
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define i32 @foo(i32 %a, i32 %b) {
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entry:
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; CHECK: foo
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@ -182,4 +185,56 @@ define i32 @f18(i32 %a, i16 %x, i32 %y) {
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ret i32 %tmp5
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}
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declare void @llvm.trap() nounwind
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define i32 @f19(i32 %x) {
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; CHECK: f19
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; CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1]
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%tmp.1 = call i32 @llvm.ctlz.i32( i32 %x )
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ret i32 %tmp.1
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}
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define i32 @f20(i32 %X) {
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; CHECK: f20
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; CHECK: rev16 r0, r0 @ encoding: [0xb0,0x0f,0xbf,0xe6]
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%tmp1 = lshr i32 %X, 8
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%X15 = bitcast i32 %X to i32
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%tmp4 = shl i32 %X15, 8
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%tmp2 = and i32 %tmp1, 16711680
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%tmp5 = and i32 %tmp4, -16777216
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%tmp9 = and i32 %tmp1, 255
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%tmp13 = and i32 %tmp4, 65280
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%tmp6 = or i32 %tmp5, %tmp2
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%tmp10 = or i32 %tmp6, %tmp13
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%tmp14 = or i32 %tmp10, %tmp9
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ret i32 %tmp14
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}
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define i32 @f21(i32 %X) {
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; CHECK: f21
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; CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6]
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%tmp1 = lshr i32 %X, 8
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%tmp1.upgrd.1 = trunc i32 %tmp1 to i16
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%tmp3 = trunc i32 %X to i16
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%tmp2 = and i16 %tmp1.upgrd.1, 255
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%tmp4 = shl i16 %tmp3, 8
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%tmp5 = or i16 %tmp2, %tmp4
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%tmp5.upgrd.2 = sext i16 %tmp5 to i32
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ret i32 %tmp5.upgrd.2
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}
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define i32 @f22(i32 %X, i32 %Y) {
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; CHECK: f22
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; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6]
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%tmp1 = and i32 %X, -65536
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%tmp3 = lshr i32 %Y, 22
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%tmp57 = or i32 %tmp3, %tmp1
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ret i32 %tmp57
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}
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define i32 @f23(i32 %X, i32 %Y) {
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; CHECK: f23
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; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6]
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%tmp19 = and i32 %X, 65535
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%tmp37 = shl i32 %Y, 18
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%tmp5 = or i32 %tmp37, %tmp19
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ret i32 %tmp5
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}
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