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Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly

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in the MC lowering process.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119559 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-11-17 21:05:55 +00:00
parent 6b19491468
commit f8dabac604
2 changed files with 25 additions and 12 deletions
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22
lib/Target/ARM/ARMAsmPrinter.cpp
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@@ -938,8 +938,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
case ARM::tBR_JTr:
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd: {
case ARM::BR_JTm: {
// Lower and emit the instruction itself, then the jump table following it.
MCInst TmpInst;
// FIXME: The branch instruction is really a pseudo. We should xform it
@@ -949,6 +948,25 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
EmitJumpTable(MI);
return;
}
case ARM::BR_JTadd: {
// Lower and emit the instruction itself, then the jump table following it.
// add pc, target, idx
MCInst AddInst;
AddInst.setOpcode(ARM::ADDrr);
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
// Add predicate operands.
AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
AddInst.addOperand(MCOperand::CreateReg(0));
// Add 's' bit operand (always reg0 for this)
AddInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(AddInst);
// Output the data for the jump table itself
EmitJumpTable(MI);
return;
}
case ARM::TRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.