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Move repeated code to a new method. No functional change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-12-23 21:28:23 +00:00
parent 244d7571f7
commit f8e33e513f
1 changed files with 47 additions and 17 deletions
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64
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -87,6 +87,21 @@ namespace {
int Offset, unsigned Base, bool BaseKill, int Opcode, int Offset, unsigned Base, bool BaseKill, int Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs); DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
void MergeOpsUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
int Offset,
unsigned Base,
bool BaseKill,
int Opcode,
ARMCC::CondCodes Pred,
unsigned PredReg,
unsigned Scratch,
DebugLoc dl,
SmallVector<std::pair<unsigned, bool>, 8> &Regs,
MemOpQueue &MemOps,
unsigned memOpsFrom,
unsigned memOpsTo,
SmallVector<MachineBasicBlock::iterator, 4> &Merges);
void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
int Opcode, unsigned Size, int Opcode, unsigned Size,
ARMCC::CondCodes Pred, unsigned PredReg, ARMCC::CondCodes Pred, unsigned PredReg,
@ -248,6 +263,34 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
return true; return true;
} }
// MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on
// success.
void ARMLoadStoreOpt::
MergeOpsUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
int Offset,
unsigned Base,
bool BaseKill,
int Opcode,
ARMCC::CondCodes Pred,
unsigned PredReg,
unsigned Scratch,
DebugLoc dl,
SmallVector<std::pair<unsigned, bool>, 8> &Regs,
MemOpQueue &MemOps,
unsigned memOpsFrom,
unsigned memOpsTo,
SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
if (!MergeOps(MBB, MBBI, Offset, Base, BaseKill, Opcode,
Pred, PredReg, Scratch, dl, Regs))
return;
Merges.push_back(prior(MBBI));
for (unsigned j = memOpsFrom; j < memOpsTo; ++j) {
MBB.erase(MemOps[j].MBBI);
MemOps[j].Merged = true;
}
}
/// MergeLDR_STR - Merge a number of load / store instructions into one or more /// MergeLDR_STR - Merge a number of load / store instructions into one or more
/// load / store multiple instructions. /// load / store multiple instructions.
void void
@ -282,14 +325,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
PRegNum = RegNum; PRegNum = RegNum;
} else { } else {
// Can't merge this in. Try merge the earlier ones first. // Can't merge this in. Try merge the earlier ones first.
if (MergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg, MergeOpsUpdate(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
Scratch, dl, Regs)) { Scratch, dl, Regs, MemOps, SIndex, i, Merges);
Merges.push_back(prior(Loc));
for (unsigned j = SIndex; j < i; ++j) {
MBB.erase(MemOps[j].MBBI);
MemOps[j].Merged = true;
}
}
MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch, MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
MemOps, Merges); MemOps, Merges);
return; return;
@ -302,15 +339,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
} }
bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1; bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
if (MergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg, MergeOpsUpdate(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
Scratch, dl, Regs)) { Scratch, dl, Regs, MemOps, SIndex, MemOps.size(), Merges);
Merges.push_back(prior(Loc));
for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
MBB.erase(MemOps[i].MBBI);
MemOps[i].Merged = true;
}
}
return; return;
} }