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fix PowerPC/2007-01-04-ArgExtension.ll, a bug handling K&R prototypes with

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the recent signless changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-01-04 22:22:37 +00:00
parent e0170dfd2a
commit f8e7a21912
1 changed files with 6 additions and 4 deletions
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10
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -2955,10 +2955,12 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
case Promote: {
SDOperand Op(Result, i++);
if (MVT::isInteger(VT)) {
unsigned AssertOp = ISD::AssertSext;
if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
AssertOp = ISD::AssertZext;
Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
if (FTy->paramHasAttr(Idx, FunctionType::SExtAttribute))
Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
DAG.getValueType(VT));
else if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
DAG.getValueType(VT));
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
} else {
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");