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ARM pop of a single register encodes as post-indexed LDR.

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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-08-11 17:35:48 +00:00
parent dceb002f82
commit f8fce711e8
4 changed files with 40 additions and 6 deletions
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30
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -136,6 +136,8 @@ class ARMAsmParser : public MCTargetAsmParser {
bool validateInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
void processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
public:
ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
@@ -2856,6 +2858,30 @@ validateInstruction(MCInst &Inst,
return false;
}
void ARMAsmParser::
processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
case ARM::LDMIA_UPD:
// If this is a load of a single register via a 'pop', then we should use
// a post-indexed LDR instruction instead, per the ARM ARM.
if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
Inst.getNumOperands() == 5) {
MCInst TmpInst;
TmpInst.setOpcode(ARM::LDR_POST_IMM);
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
TmpInst.addOperand(MCOperand::CreateImm(4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
}
break;
}
}
bool ARMAsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
@@ -2871,6 +2897,10 @@ MatchAndEmitInstruction(SMLoc IDLoc,
if (validateInstruction(Inst, Operands))
return true;
// Some instructions need post-processing to, for example, tweak which
// encoding is selected.
processInstruction(Inst, Operands);
Out.EmitInstruction(Inst);
return false;
case Match_MissingFeature: