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SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-09-27 18:22:18 +00:00
parent 56bc894d06
commit f90a656a9f
2 changed files with 2 additions and 2 deletions
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2
lib/Target/Sparc/SparcRegisterInfo.td
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@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td"
// FIXME: the register order should be defined in terms of the preferred // FIXME: the register order should be defined in terms of the preferred
// allocation order... // allocation order...
// //
def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5, I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7, G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7, O0, O1, O2, O3, O4, O5, O7,

2
lib/Target/SparcV8/SparcV8RegisterInfo.td
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@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td"
// FIXME: the register order should be defined in terms of the preferred // FIXME: the register order should be defined in terms of the preferred
// allocation order... // allocation order...
// //
def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5, I0, I1, I2, I3, I4, I5,
G1, G2, G3, G4, G5, G6, G7, G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O7, O0, O1, O2, O3, O4, O5, O7,