From f91c14920c8cb66195380b5f83e8a98852bedd6a Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 11 Aug 2011 19:26:17 +0000 Subject: [PATCH] ARM STR(register) assembly parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/arm-memory-instructions.s | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s index 92180a0e54c..5cb09b915c5 100644 --- a/test/MC/ARM/arm-memory-instructions.s +++ b/test/MC/ARM/arm-memory-instructions.s @@ -307,3 +307,30 @@ _func: @ CHECK: str r3, [r5, #40]! @ encoding: [0x28,0x30,0xa5,0xe5] @ CHECK: str r9, [sp], #4095 @ encoding: [0xff,0x9f,0x8d,0xe4] @ CHECK: str r1, [r7], #-128 @ encoding: [0x80,0x10,0x07,0xe4] + + +@------------------------------------------------------------------------------ +@ FIXME: STR (literal) +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ STR (register) +@------------------------------------------------------------------------------ + str r9, [r6, r3] + str r8, [r0, -r2] + str r7, [r1, r6]! + str r6, [sp, -r1]! + str r5, [r3], r9 + str r4, [r2], -r5 + str r3, [r4, -r2, lsl #2] + str r2, [r7], r3, asr #24 + +@ CHECK: str r9, [r6, r3] @ encoding: [0x03,0x90,0x86,0xe7] +@ CHECK: str r8, [r0, -r2] @ encoding: [0x02,0x80,0x00,0xe7] +@ CHECK: str r7, [r1, r6]! @ encoding: [0x06,0x70,0xa1,0xe7] +@ CHECK: str r6, [sp, -r1]! @ encoding: [0x01,0x60,0x2d,0xe7] +@ CHECK: str r5, [r3], r9 @ encoding: [0x09,0x50,0x83,0xe6] +@ CHECK: str r4, [r2], -r5 @ encoding: [0x05,0x40,0x02,0xe6] +@ CHECK: str r3, [r4, -r2, lsl #2] @ encoding: [0x02,0x31,0x04,0xe7] +@ CHECK: str r2, [r7], r3, asr #24 @ encoding: [0x43,0x2c,0x87,0xe6] +