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Handled unaligned load/stores properly in Mips16

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Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163956 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-09-15 01:02:03 +00:00
parent 062986c2f0
commit f934d159ae
2 changed files with 22 additions and 2 deletions
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9
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -161,8 +161,10 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
setOperationAction(ISD::LOAD, MVT::i32, Custom);
setOperationAction(ISD::STORE, MVT::i32, Custom);
if (!Subtarget->inMips16Mode()) {
setOperationAction(ISD::LOAD, MVT::i32, Custom);
setOperationAction(ISD::STORE, MVT::i32, Custom);
}
if (!TM.Options.NoNaNsFPMath) {
setOperationAction(ISD::FABS, MVT::f32, Custom);
@ -309,6 +311,9 @@ MipsTargetLowering(MipsTargetMachine &TM)
bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
if (Subtarget->inMips16Mode())
return false;
switch (SVT) {
case MVT::i64:
case MVT::i32:

15
test/CodeGen/Mips/ul1.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
%struct.ua = type <{ i16, i32 }>
@foo = common global %struct.ua zeroinitializer, align 1
define i32 @main() nounwind {
entry:
store i32 10, i32* getelementptr inbounds (%struct.ua* @foo, i32 0, i32 1), align 1
; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
; 16: sb ${{[0-9]+}}, {{[0-9]+}}(${{[0-9]+}})
ret i32 0
}