mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
d0b5c65b16
commit
f93b863066
@ -16,8 +16,6 @@
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#include "MipsAsmPrinter.h"
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsMCInstLower.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/ADT/SmallString.h"
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@ -45,24 +43,23 @@
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using namespace llvm;
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static bool isUnalignedLoadStore(unsigned Opc) {
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return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
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Opc == Mips::USW || Opc == Mips::USH ||
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Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
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Opc == Mips::USW_P8 || Opc == Mips::USH_P8 ||
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Opc == Mips::ULD || Opc == Mips::ULW64 || Opc == Mips::ULH64 ||
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Opc == Mips::ULHu64 || Opc == Mips::USD || Opc == Mips::USW64 ||
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Opc == Mips::USH64 ||
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Opc == Mips::ULD_P8 || Opc == Mips::ULW64_P8 ||
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Opc == Mips::ULH64_P8 || Opc == Mips::ULHu64_P8 ||
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Opc == Mips::USD_P8 || Opc == Mips::USW64_P8 ||
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Opc == Mips::USH64_P8;
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void MipsAsmPrinter::EmitInstrWithMacroNoAT(const MachineInstr *MI) {
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tat"));
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OutStreamer.EmitInstruction(TmpInst);
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
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}
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static bool isDirective(unsigned Opc) {
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return Opc == Mips::MACRO || Opc == Mips::NOMACRO ||
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Opc == Mips::REORDER || Opc == Mips::NOREORDER ||
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Opc == Mips::ATMACRO || Opc == Mips::NOAT;
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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AsmPrinter::runOnMachineFunction(MF);
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return true;
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}
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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@ -74,49 +71,70 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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MipsMCInstLower MCInstLowering(Mang, *MF, *this);
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unsigned Opc = MI->getOpcode();
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MCInst TmpInst0;
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SmallVector<MCInst, 4> MCInsts;
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MCInstLowering.Lower(MI, TmpInst0);
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if (!OutStreamer.hasRawTextSupport() && isDirective(Opc))
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return;
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// Enclose unaligned load or store with .macro & .nomacro directives.
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if (isUnalignedLoadStore(Opc)) {
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switch (Opc) {
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case Mips::ULW:
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case Mips::ULH:
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case Mips::ULHu:
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case Mips::USW:
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case Mips::USH:
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case Mips::ULW_P8:
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case Mips::ULH_P8:
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case Mips::ULHu_P8:
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case Mips::USW_P8:
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case Mips::USH_P8:
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case Mips::ULD:
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case Mips::ULW64:
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case Mips::ULH64:
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case Mips::ULHu64:
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case Mips::USD:
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case Mips::USW64:
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case Mips::USH64:
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case Mips::ULD_P8:
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case Mips::ULW64_P8:
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case Mips::ULH64_P8:
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case Mips::ULHu64_P8:
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case Mips::USD_P8:
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case Mips::USW64_P8:
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case Mips::USH64_P8: {
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if (OutStreamer.hasRawTextSupport()) {
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MCInst Directive;
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Directive.setOpcode(Mips::MACRO);
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OutStreamer.EmitInstruction(Directive);
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OutStreamer.EmitInstruction(TmpInst0);
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Directive.setOpcode(Mips::NOMACRO);
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OutStreamer.EmitInstruction(Directive);
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} else {
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MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
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!= MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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EmitInstrWithMacroNoAT(MI);
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return;
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}
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MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
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!= MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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return;
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}
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case Mips::CPRESTORE: {
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
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int64_t Offset = MO.getImm();
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if (!OutStreamer.hasRawTextSupport()) {
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// Lower CPLOAD and CPRESTORE
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if (Opc == Mips::CPLOAD)
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MCInstLowering.LowerCPLOAD(MI, MCInsts);
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else if (Opc == Mips::CPRESTORE)
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MCInstLowering.LowerCPRESTORE(MI, MCInsts);
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if (OutStreamer.hasRawTextSupport()) {
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if (!isInt<16>(Offset)) {
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EmitInstrWithMacroNoAT(MI);
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return;
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}
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} else {
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MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
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if (!MCInsts.empty()) {
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
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I != MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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return;
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}
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}
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if (Opc == Mips::SETGP01) {
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break;
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}
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case Mips::SETGP01: {
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MCInstLowering.LowerSETGP01(MI, MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
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@ -125,7 +143,11 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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default:
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break;
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}
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MCInstLowering.Lower(MI, TmpInst0);
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OutStreamer.EmitInstruction(TmpInst0);
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}
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@ -269,13 +291,35 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() {
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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MCInstLowering.Initialize(Mang, &MF->getContext());
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emitFrameDirective();
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bool EmitCPLoad = (MF->getTarget().getRelocationModel() == Reloc::PIC_) &&
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Subtarget->isABI_O32() && MipsFI->globalBaseRegSet() &&
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MipsFI->globalBaseRegFixed();
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if (OutStreamer.hasRawTextSupport()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printSavedRegsBitmask(OS);
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OutStreamer.EmitRawText(OS.str());
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OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
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// Emit .cpload directive if needed.
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if (EmitCPLoad)
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OutStreamer.EmitRawText(StringRef("\t.cpload\t$25"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
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} else if (EmitCPLoad) {
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SmallVector<MCInst, 4> MCInsts;
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MCInstLowering.LowerCPLOAD(MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
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I != MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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}
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}
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@ -286,6 +330,9 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
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// always be at the function end, and we can't emit and
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// break with BB logic.
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if (OutStreamer.hasRawTextSupport()) {
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tat"));
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
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OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
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@ -14,6 +14,8 @@
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#ifndef MIPSASMPRINTER_H
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#define MIPSASMPRINTER_H
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#include "MipsMachineFunction.h"
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#include "MipsMCInstLower.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/Support/Compiler.h"
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@ -28,12 +30,16 @@ class raw_ostream;
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class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
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void EmitInstrWithMacroNoAT(const MachineInstr *MI);
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public:
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const MipsSubtarget *Subtarget;
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const MipsFunctionInfo *MipsFI;
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MipsMCInstLower MCInstLowering;
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explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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: AsmPrinter(TM, Streamer), MCInstLowering(*this) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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}
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@ -41,6 +47,8 @@ public:
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return "Mips Assembly Printer";
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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void EmitInstruction(const MachineInstr *MI);
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void printSavedRegsBitmask(raw_ostream &O);
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void printHex32(unsigned int Value, raw_ostream &O);
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@ -108,9 +108,6 @@ static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64,
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AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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@ -127,7 +124,6 @@ static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64,
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg);
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BuildMI(MBB, II, DL, TII.get(Mips::ATMACRO));
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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@ -159,18 +155,22 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Update stack size
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MFI->setStackSize(StackSize);
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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// Emit instructions that set the global base register if the target ABI is
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// O32.
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if (isPIC && MipsFI->globalBaseRegSet() && STI.isABI_O32()) {
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if (MipsFI->globalBaseRegFixed())
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BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD))
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.addReg(RegInfo->getPICCallReg());
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else
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if (isPIC && MipsFI->globalBaseRegSet() && STI.isABI_O32() &&
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!MipsFI->globalBaseRegFixed()) {
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// See MipsInstrInfo.td for explanation.
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BuildMI(MBB, MBBI, dl, TII.get(Mips:: SETGP01), Mips::V0);
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MachineBasicBlock *NewEntry = MF.CreateMachineBasicBlock();
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MF.insert(&MBB, NewEntry);
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NewEntry->addSuccessor(&MBB);
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// Copy live in registers.
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for (MachineBasicBlock::livein_iterator R = MBB.livein_begin();
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R != MBB.livein_end(); ++R)
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NewEntry->addLiveIn(*R);
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BuildMI(*NewEntry, NewEntry->begin(), dl, TII.get(Mips:: SETGP01),
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Mips::V0);
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}
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// No need to allocate space on the stack.
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@ -183,8 +183,10 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Adjust stack.
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if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize)
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
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else // Expand immediate that doesn't fit in 16-bit.
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else { // Expand immediate that doesn't fit in 16-bit.
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MipsFI->setEmitNOAT();
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expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
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}
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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@ -254,12 +256,8 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Restore GP from the saved stack location
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if (MipsFI->needGPSaveRestore()) {
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unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI());
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset);
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if (Offset >= 0x8000) {
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BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO));
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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}
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset)
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.addReg(Mips::GP);
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}
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}
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@ -727,24 +727,13 @@ def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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// Some assembly macros need to avoid pseudoinstructions and assembler
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// automatic reodering, we should reorder ourselves.
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def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
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def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
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def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
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def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
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// These macros are inserted to prevent GAS from complaining
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// when using the AT register.
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def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
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def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
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let neverHasSideEffects = 1 in
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
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".cprestore\t$loc", []>;
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// For O32 ABI & PIC & non-fixed global base register, the following instruction
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// seqeunce is emitted to set the global base register:
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@ -762,7 +751,10 @@ def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
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// before or between instructions 0 and 1, which is a limitation imposed by
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// GNU linker.
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let isTerminator = 1, isBarrier = 1 in
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def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
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let neverHasSideEffects = 1 in
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def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
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[]>;
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@ -26,9 +26,13 @@
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using namespace llvm;
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MipsMCInstLower::MipsMCInstLower(Mangler *mang, const MachineFunction &mf,
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MipsAsmPrinter &asmprinter)
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: Ctx(mf.getContext()), Mang(mang), AsmPrinter(asmprinter) {}
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MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
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: AsmPrinter(asmprinter) {}
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void MipsMCInstLower::Initialize(Mangler *M, MCContext* C) {
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Mang = M;
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Ctx = C;
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}
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MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MachineOperandType MOTy,
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@ -90,7 +94,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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llvm_unreachable("<unknown operand type>");
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}
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
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if (!Offset)
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return MCOperand::CreateExpr(MCSym);
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@ -98,76 +102,68 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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// Assume offset is never negative.
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assert(Offset > 0);
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const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx);
|
||||
const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
|
||||
const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
|
||||
return MCOperand::CreateExpr(AddExpr);
|
||||
}
|
||||
|
||||
static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0,
|
||||
const MCOperand& Opnd1,
|
||||
const MCOperand& Opnd2 = MCOperand()) {
|
||||
Inst.setOpcode(Opc);
|
||||
Inst.addOperand(Opnd0);
|
||||
Inst.addOperand(Opnd1);
|
||||
if (Opnd2.isValid())
|
||||
Inst.addOperand(Opnd2);
|
||||
}
|
||||
|
||||
// Lower ".cpload $reg" to
|
||||
// "lui $gp, %hi(_gp_disp)"
|
||||
// "addiu $gp, $gp, %lo(_gp_disp)"
|
||||
// "addu $gp. $gp, $reg"
|
||||
void MipsMCInstLower::LowerCPLOAD(const MachineInstr *MI,
|
||||
SmallVector<MCInst, 4>& MCInsts) {
|
||||
MCInst Lui, Addiu, Addu;
|
||||
// "addu $gp, $gp, $t9"
|
||||
void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
|
||||
MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
|
||||
MCOperand T9Reg = MCOperand::CreateReg(Mips::T9);
|
||||
StringRef SymName("_gp_disp");
|
||||
const MCSymbol *Symbol = Ctx.GetOrCreateSymbol(SymName);
|
||||
const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
|
||||
const MCSymbolRefExpr *MCSym;
|
||||
|
||||
// lui $gp, %hi(_gp_disp)
|
||||
Lui.setOpcode(Mips::LUi);
|
||||
Lui.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx);
|
||||
Lui.addOperand(MCOperand::CreateExpr(MCSym));
|
||||
MCInsts.push_back(Lui);
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
|
||||
MCOperand SymHi = MCOperand::CreateExpr(MCSym);
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
|
||||
MCOperand SymLo = MCOperand::CreateExpr(MCSym);
|
||||
|
||||
// addiu $gp, $gp, %lo(_gp_disp)
|
||||
Addiu.setOpcode(Mips::ADDiu);
|
||||
Addiu.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
Addiu.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx);
|
||||
Addiu.addOperand(MCOperand::CreateExpr(MCSym));
|
||||
MCInsts.push_back(Addiu);
|
||||
MCInsts.resize(3);
|
||||
|
||||
// addu $gp. $gp, $reg
|
||||
Addu.setOpcode(Mips::ADDu);
|
||||
Addu.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
Addu.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
const MachineOperand &MO = MI->getOperand(0);
|
||||
assert(MO.isReg() && "CPLOAD's operand must be a register.");
|
||||
Addu.addOperand(MCOperand::CreateReg(MO.getReg()));
|
||||
MCInsts.push_back(Addu);
|
||||
CreateMCInst(MCInsts[0], Mips::LUi, GPReg, SymHi);
|
||||
CreateMCInst(MCInsts[1], Mips::ADDiu, GPReg, GPReg, SymLo);
|
||||
CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
|
||||
}
|
||||
|
||||
// Lower ".cprestore offset" to "sw $gp, offset($sp)".
|
||||
void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
|
||||
void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
|
||||
SmallVector<MCInst, 4>& MCInsts) {
|
||||
const MachineOperand &MO = MI->getOperand(0);
|
||||
assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
|
||||
unsigned Offset = MO.getImm(), Reg = Mips::SP;
|
||||
MCInst Sw;
|
||||
assert(isInt<32>(Offset) && (Offset >= 0) &&
|
||||
"Imm operand of .cprestore must be a non-negative 32-bit value.");
|
||||
|
||||
if (Offset >= 0x8000) {
|
||||
unsigned Hi = (Offset >> 16) + ((Offset & 0x8000) != 0);
|
||||
MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
|
||||
MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
|
||||
|
||||
if (!isInt<16>(Offset)) {
|
||||
unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
|
||||
Offset &= 0xffff;
|
||||
Reg = Mips::AT;
|
||||
MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
|
||||
BaseReg = ATReg;
|
||||
|
||||
// lui at,hi
|
||||
// addu at,at,sp
|
||||
MCInsts.resize(2);
|
||||
MCInsts[0].setOpcode(Mips::LUi);
|
||||
MCInsts[0].addOperand(MCOperand::CreateReg(Mips::AT));
|
||||
MCInsts[0].addOperand(MCOperand::CreateImm(Hi));
|
||||
MCInsts[1].setOpcode(Mips::ADDu);
|
||||
MCInsts[1].addOperand(MCOperand::CreateReg(Mips::AT));
|
||||
MCInsts[1].addOperand(MCOperand::CreateReg(Mips::AT));
|
||||
MCInsts[1].addOperand(MCOperand::CreateReg(Mips::SP));
|
||||
CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
|
||||
CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
|
||||
}
|
||||
|
||||
Sw.setOpcode(Mips::SW);
|
||||
Sw.addOperand(MCOperand::CreateReg(Mips::GP));
|
||||
Sw.addOperand(MCOperand::CreateReg(Reg));
|
||||
Sw.addOperand(MCOperand::CreateImm(Offset));
|
||||
MCInst Sw;
|
||||
CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
|
||||
MCInsts.push_back(Sw);
|
||||
}
|
||||
|
||||
@ -332,18 +328,16 @@ void MipsMCInstLower::LowerSETGP01(const MachineInstr *MI,
|
||||
assert(MO.isReg());
|
||||
MCOperand RegOpnd = MCOperand::CreateReg(MO.getReg());
|
||||
StringRef SymName("_gp_disp");
|
||||
const MCSymbol *Sym = Ctx.GetOrCreateSymbol(SymName);
|
||||
const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
|
||||
const MCSymbolRefExpr *MCSym;
|
||||
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
|
||||
MCOperand SymHi = MCOperand::CreateExpr(MCSym);
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
|
||||
MCOperand SymLo = MCOperand::CreateExpr(MCSym);
|
||||
|
||||
MCInsts.resize(2);
|
||||
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx);
|
||||
MCInsts[0].setOpcode(Mips::LUi);
|
||||
MCInsts[0].addOperand(RegOpnd);
|
||||
MCInsts[0].addOperand(MCOperand::CreateExpr(MCSym));
|
||||
MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx);
|
||||
MCInsts[1].setOpcode(Mips::ADDiu);
|
||||
MCInsts[1].addOperand(RegOpnd);
|
||||
MCInsts[1].addOperand(RegOpnd);
|
||||
MCInsts[1].addOperand(MCOperand::CreateExpr(MCSym));
|
||||
CreateMCInst(MCInsts[0], Mips::LUi, RegOpnd, SymHi);
|
||||
CreateMCInst(MCInsts[1], Mips::ADDiu, RegOpnd, RegOpnd, SymLo);
|
||||
}
|
||||
|
||||
@ -26,15 +26,15 @@ namespace llvm {
|
||||
// MCInst.
|
||||
class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
|
||||
typedef MachineOperand::MachineOperandType MachineOperandType;
|
||||
MCContext &Ctx;
|
||||
MCContext *Ctx;
|
||||
Mangler *Mang;
|
||||
MipsAsmPrinter &AsmPrinter;
|
||||
public:
|
||||
MipsMCInstLower(Mangler *mang, const MachineFunction &MF,
|
||||
MipsAsmPrinter &asmprinter);
|
||||
MipsMCInstLower(MipsAsmPrinter &asmprinter);
|
||||
void Initialize(Mangler *mang, MCContext* C);
|
||||
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
|
||||
void LowerCPLOAD(const MachineInstr *MI, SmallVector<MCInst, 4>& MCInsts);
|
||||
void LowerCPRESTORE(const MachineInstr *MI, SmallVector<MCInst, 4>& MCInsts);
|
||||
void LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts);
|
||||
void LowerCPRESTORE(int64_t Offset, SmallVector<MCInst, 4>& MCInsts);
|
||||
void LowerUnalignedLoadStore(const MachineInstr *MI,
|
||||
SmallVector<MCInst, 4>& MCInsts);
|
||||
void LowerSETGP01(const MachineInstr *MI, SmallVector<MCInst, 4>& MCInsts);
|
||||
|
||||
@ -227,8 +227,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
|
||||
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
|
||||
|
||||
// FIXME: change this when mips goes MC".
|
||||
BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
|
||||
MipsFI->setEmitNOAT();
|
||||
|
||||
// The first instruction can be a LUi, which is different from other
|
||||
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
||||
@ -249,7 +248,6 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
|
||||
FrameReg = ATReg;
|
||||
Offset = SignExtend64<16>(Inst->ImmOpnd);
|
||||
BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
|
||||
}
|
||||
|
||||
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user