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Remove xs1b predicate since it is no longer needed to differentiate betweem

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xs1a and xs1b.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2009-10-06 16:17:57 +00:00
parent 34bee6da7a
commit f9416ea0cd
4 changed files with 5 additions and 33 deletions
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12
lib/Target/XCore/XCore.td
View File

@ -29,14 +29,6 @@ def XCoreInstrInfo : InstrInfo {
let TSFlagsShifts = [];
}
//===----------------------------------------------------------------------===//
// XCore Subtarget features.
//===----------------------------------------------------------------------===//
def FeatureXS1B
: SubtargetFeature<"xs1b", "IsXS1B", "true",
"Enable XS1B instructions">;
//===----------------------------------------------------------------------===//
// XCore processors supported.
//===----------------------------------------------------------------------===//
@ -44,8 +36,8 @@ def FeatureXS1B
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"generic", [FeatureXS1B]>;
def : Proc<"xs1b-generic", [FeatureXS1B]>;
def : Proc<"generic", []>;
def : Proc<"xs1b-generic", []>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing

17
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -22,14 +22,6 @@
include "XCoreInstrFormats.td"
//===----------------------------------------------------------------------===//
// Feature predicates.
//===----------------------------------------------------------------------===//
// HasXS1B - This predicate is true when the target processor supports XS1B
// instructions.
def HasXS1B : Predicate<"Subtarget.isXS1B()">;
//===----------------------------------------------------------------------===//
// XCore specific DAG Nodes.
//
@ -473,7 +465,7 @@ def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
}
// Four operand long
let Predicates = [HasXS1B], Constraints = "$src1 = $dst1,$src2 = $dst2" in {
let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
GRRegs:$src4),
@ -489,7 +481,6 @@ def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
// Five operand long
let Predicates = [HasXS1B] in {
def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"ladd $dst1, $dst2, $src1, $src2, $src3",
@ -504,7 +495,6 @@ def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"ldiv $dst1, $dst2, $src1, $src2, $src3",
[]>;
}
// Six operand long
@ -661,13 +651,12 @@ def BRFU_lu6 : _FLU6<
}
//let Uses = [CP] in ...
let Predicates = [HasXS1B], Defs = [R11], neverHasSideEffects = 1,
isReMaterializable = 1 in
let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
"ldaw r11, cp[$a]",
[]>;
let Predicates = [HasXS1B], Defs = [R11], isReMaterializable = 1 in
let Defs = [R11], isReMaterializable = 1 in
def LDAWCP_lu6: _FLRU6<
(outs), (ins MEMii:$a),
"ldaw r11, cp[$a]",

6
lib/Target/XCore/XCoreSubtarget.cpp
View File

@ -13,14 +13,8 @@
#include "XCoreSubtarget.h"
#include "XCore.h"
#include "XCoreGenSubtarget.inc"
using namespace llvm;
XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS)
: IsXS1B(false)
{
std::string CPU = "xs1b-generic";
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
}

3
lib/Target/XCore/XCoreSubtarget.h
View File

@ -22,15 +22,12 @@
namespace llvm {
class XCoreSubtarget : public TargetSubtarget {
bool IsXS1B;
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
///
XCoreSubtarget(const std::string &TT, const std::string &FS);
bool isXS1B() const { return IsXS1B; }
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.