From f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa Mon Sep 17 00:00:00 2001
From: Andrew Trick <atrick@apple.com>
Date: Tue, 5 Jun 2012 03:44:43 +0000
Subject: [PATCH] ARM itinerary properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMScheduleA8.td |  6 +++++-
 lib/Target/ARM/ARMScheduleA9.td |  6 +++++-
 lib/Target/ARM/ARMSubtarget.cpp | 20 --------------------
 3 files changed, 10 insertions(+), 22 deletions(-)

diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index 8b1fb9386ad..eb1083ca23f 100644
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -22,7 +22,11 @@ def A8_NLSPipe : FuncUnit; // NEON LS pipe
 //
 // Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
 //
-def CortexA8Itineraries : ProcessorItineraries<
+def CortexA8Itineraries : MultiIssueItineraries<
+  2,  // IssueWidth
+  -1, // MinLatency - OperandCycles are interpreted as MinLatency.
+  2,  // LoadLatency - overriden by OperandCycles.
+  10, // HighLatency - currently unused.
   [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
   [], [
   // Two fully-pipelined integer ALU pipelines
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index 0d710cc1ace..a00577bf3d3 100644
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -31,7 +31,11 @@ def A9_DRegsN  : FuncUnit; // FP register set, NEON side
 // Bypasses
 def A9_LdBypass : Bypass;
 
-def CortexA9Itineraries : ProcessorItineraries<
+def CortexA9Itineraries : MultiIssueItineraries<
+  2, // IssueWidth - FIXME: A9_Issue0, A9_Issue1 are now redundant.
+  0, // MinLatency - FIXME: for misched, remove InstrStage for OOO operations.
+  2, // LoadLatency - optimistic, assumes bypass, overriden by OperandCycles.
+  10, // HighLatency - currently unused.
   [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
    A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
   [A9_LdBypass], [
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 0bea9e4b2b9..db6512c9b96 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -100,9 +100,6 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
-  // After parsing Itineraries, set ItinData.IssueWidth.
-  computeIssueWidth();
-
   if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
     // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
     // Darwin-EABI conforms to AACPS but not the rest of EABI.
@@ -193,23 +190,6 @@ unsigned ARMSubtarget::getMispredictionPenalty() const {
   return 10;
 }
 
-void ARMSubtarget::computeIssueWidth() {
-  unsigned allStage1Units = 0;
-  for (const InstrItinerary *itin = InstrItins.Itineraries;
-       itin->FirstStage != ~0U; ++itin) {
-    const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
-    allStage1Units |= IS->getUnits();
-  }
-  InstrItins.Props.IssueWidth = 0;
-  while (allStage1Units) {
-    ++InstrItins.Props.IssueWidth;
-    // clear the lowest bit
-    allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
-  }
-  assert(InstrItins.Props.IssueWidth <= 2 &&
-         "itinerary bug, too many stage 1 units");
-}
-
 bool ARMSubtarget::enablePostRAScheduler(
            CodeGenOpt::Level OptLevel,
            TargetSubtargetInfo::AntiDepBreakMode& Mode,