6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00
Code Issues Projects Releases Wiki Activity

Compile X > -1 -> text X,X; js dest

Browse Source 
This implements CodeGen/X86/jump_sign.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-09-13 03:22:10 +00:00
parent 06f7ee9133
commit f95705163f
2 changed files with 23 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/README.txt
View File

@ -630,15 +630,3 @@ This saves a movzbl, and saves a truncate if it doesn't get coallesced right.
This is a simple DAGCombine to propagate the zext through the and. This is a simple DAGCombine to propagate the zext through the and.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
Instead of:
cmpl $4294967295, %edx
jg LBB1_8 #cond_false49
emit:
testl %edx, %edx
js LBB1_8
This saves a byte of code space.

39
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1866,13 +1866,23 @@ static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
/// specific condition code. It returns a false if it cannot do a direct /// specific condition code. It returns a false if it cannot do a direct
/// translation. X86CC is the translated CondCode. Flip is set to true if the /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
/// the order of comparison operands should be flipped. /// needed.
static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
unsigned &X86CC, bool &Flip) { unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
Flip = false; SelectionDAG &DAG) {
X86CC = X86ISD::COND_INVALID; X86CC = X86ISD::COND_INVALID;
if (!isFP) { if (!isFP) {
if (SetCCOpcode == ISD::SETGT) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
if (RHSC->isAllOnesValue()) {
// X > -1 -> X == 0, jump on sign.
RHS = DAG.getConstant(0, RHS.getValueType());
X86CC = X86ISD::COND_S;
return true;
}
}
switch (SetCCOpcode) { switch (SetCCOpcode) {
default: break; default: break;
case ISD::SETEQ: X86CC = X86ISD::COND_E; break; case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
@ -1893,6 +1903,7 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
// 0 | 0 | 1 | X < Y // 0 | 0 | 1 | X < Y
// 1 | 0 | 0 | X == Y // 1 | 0 | 0 | X == Y
// 1 | 1 | 1 | unordered // 1 | 1 | 1 | unordered
bool Flip = false;
switch (SetCCOpcode) { switch (SetCCOpcode) {
default: break; default: break;
case ISD::SETUEQ: case ISD::SETUEQ:
@ -1914,16 +1925,13 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
case ISD::SETUO: X86CC = X86ISD::COND_P; break; case ISD::SETUO: X86CC = X86ISD::COND_P; break;
case ISD::SETO: X86CC = X86ISD::COND_NP; break; case ISD::SETO: X86CC = X86ISD::COND_NP; break;
} }
if (Flip)
std::swap(LHS, RHS);
} }
return X86CC != X86ISD::COND_INVALID; return X86CC != X86ISD::COND_INVALID;
} }
static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
bool &Flip) {
return translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, Flip);
}
/// hasFPCMov - is there a floating point cmov for the specific X86 condition /// hasFPCMov - is there a floating point cmov for the specific X86 condition
/// code. Current x86 isa includes the following FP cmov instructions: /// code. Current x86 isa includes the following FP cmov instructions:
/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
@ -3620,12 +3628,11 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
bool Flip;
unsigned X86CC; unsigned X86CC;
VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
if (translateX86CC(CC, isFP, X86CC, Flip)) { if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
if (Flip) std::swap(Op0, Op1); Op0, Op1, DAG)) {
SDOperand Ops1[] = { Chain, Op0, Op1 }; SDOperand Ops1[] = { Chain, Op0, Op1 };
Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops1, 3).getValue(1); Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops1, 3).getValue(1);
SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
@ -4356,13 +4363,13 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
break; break;
} }
bool Flip;
unsigned X86CC; unsigned X86CC;
translateX86CC(CC, true, X86CC, Flip); SDOperand LHS = Op.getOperand(1);
SDOperand RHS = Op.getOperand(2);
translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
SDOperand Ops1[] = { DAG.getEntryNode(), Op.getOperand(Flip?2:1), SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
Op.getOperand(Flip?1:2) };
SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3); SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };