From f95aaf951b628621c9c74bed6c450b8a52a1ae1e Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Wed, 24 Aug 2011 18:19:42 +0000
Subject: [PATCH] Add missing explicit writeback operand to tSTMIA_UPD.

rdar://10014745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrThumb.td           | 7 ++++---
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 3b2f0287106..61b94ccef7e 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -726,9 +726,10 @@ def tLDMIA_UPD :
 
 // There is no non-writeback version of STM for Thumb.
 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
-def tSTMIA_UPD : T1I<(outs),
-                     (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-                     IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
+def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
+                         (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
+                         AddrModeNone, 2, IIC_iStore_mu,
+                         "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
                      T1Encoding<{1,1,0,0,0,?}> {
   bits<3> Rn;
   bits<8> regs;
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index b76ba3e50ae..32a4fbbb01f 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3152,7 +3152,7 @@ validateInstruction(MCInst &Inst,
   }
   case ARM::tSTMIA_UPD: {
     bool listContainsBase;
-    if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
+    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
       return Error(Operands[4]->getStartLoc(),
                    "registers must be in range r0-r7");
     break;