mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-20 09:24:58 +00:00
Set ISD::FPOW to Expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42881 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e54be10418
commit
f96e4de403
@ -240,7 +240,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
|
||||
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
|
||||
|
||||
// We don't support sin/cos/fmod/copysign
|
||||
// We don't support sin/cos/fmod/copysign/pow
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
@ -249,6 +249,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
|
||||
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
|
||||
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
|
||||
|
@ -93,7 +93,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
||||
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
|
||||
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
|
||||
|
||||
// We don't support sin/cos/sqrt
|
||||
// We don't support sin/cos/sqrt/pow
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
@ -101,6 +101,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
||||
|
||||
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
|
||||
setOperationAction(ISD::SETCC, MVT::f32, Promote);
|
||||
|
||||
|
@ -73,13 +73,15 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
|
||||
setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
|
||||
|
||||
// We don't support sin/cos/sqrt
|
||||
// We don't support sin/cos/sqrt/pow
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
|
||||
// FIXME: IA64 supports fcopysign natively!
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
||||
|
@ -101,13 +101,15 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
|
||||
setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
|
||||
setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
|
||||
|
||||
// We don't support sin/cos/sqrt/fmod
|
||||
// We don't support sin/cos/sqrt/fmod/pow
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
|
||||
// If we're enabling GP optimizations, use hardware square root
|
||||
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
|
||||
|
@ -205,6 +205,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
||||
|
||||
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
|
||||
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
|
||||
|
@ -440,6 +440,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::FCOS , MVT::f80 , Expand);
|
||||
}
|
||||
|
||||
// Always use a library call for pow.
|
||||
setOperationAction(ISD::FPOW , MVT::f32 , Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f64 , Expand);
|
||||
setOperationAction(ISD::FPOW , MVT::f80 , Expand);
|
||||
|
||||
// First set operation action for all vector types to expand. Then we
|
||||
// will selectively turn on ones that can be effectively codegen'd.
|
||||
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
|
||||
@ -471,6 +476,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
|
||||
setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
|
||||
setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
|
||||
setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
|
||||
}
|
||||
|
||||
if (Subtarget->hasMMX()) {
|
||||
|
Loading…
Reference in New Issue
Block a user