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Start of generalized call support for ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115203 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -110,6 +110,7 @@ class ARMFastISel : public FastISel {
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// Backend specific FastISel code.
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virtual bool TargetSelectInstruction(const Instruction *I);
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virtual unsigned TargetMaterializeConstant(const Constant *C);
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virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
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#include "ARMGenFastISel.inc"
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@ -125,6 +126,7 @@ class ARMFastISel : public FastISel {
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virtual bool SelectSIToFP(const Instruction *I);
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virtual bool SelectFPToSI(const Instruction *I);
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virtual bool SelectSDiv(const Instruction *I);
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virtual bool SelectCall(const Instruction *I);
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// Utility routines.
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private:
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@ -455,6 +457,32 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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return ARMMaterializeInt(C, VT);
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}
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unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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// Don't handle dynamic allocas.
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if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
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EVT VT;
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if (!isTypeLegal(AI->getType(), VT)) return false;
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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// This will get lowered later into the correct offsets and registers
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// via rewriteXFrameIndex.
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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TargetRegisterClass* RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(SI->second)
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.addImm(0));
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return ResultReg;
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}
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return 0;
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}
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bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
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VT = TLI.getValueType(Ty, true);
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@ -1070,19 +1098,19 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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unsigned Arg = ArgRegs[VA.getValNo()];
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EVT ArgVT = ArgVTs[VA.getValNo()];
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// Should we ever have to promote?
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// Handle arg promotion, etc.
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switch (VA.getLocInfo()) {
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case CCValAssign::Full: break;
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default:
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assert(false && "Handle arg promotion for libcalls?");
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assert(false && "Handle arg promotion.");
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return false;
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}
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// Now copy/store arg to correct locations.
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if (VA.isRegLoc()) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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VA.getLocReg())
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.addReg(Arg);
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VA.getLocReg())
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.addReg(Arg);
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RegArgs.push_back(VA.getLocReg());
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} else {
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// Need to store
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@ -1230,6 +1258,118 @@ bool ARMFastISel::SelectSDiv(const Instruction *I) {
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return ARMEmitLibcall(I, LC);
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}
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bool ARMFastISel::SelectCall(const Instruction *I) {
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const CallInst *CI = cast<CallInst>(I);
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const Value *Callee = CI->getCalledValue();
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// Can't handle inline asm or worry about intrinsics yet.
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if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
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// Only handle global variable Callees
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const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
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if (!GV) return false;
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// Check the calling convention.
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ImmutableCallSite CS(CI);
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CallingConv::ID CC = CS.getCallingConv();
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// TODO: Avoid some calling conventions?
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if (CC != CallingConv::C) {
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errs() << "Can't handle calling convention: " << CC << "\n";
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return false;
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}
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// Let SDISel handle vararg functions.
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const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
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const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
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if (FTy->isVarArg())
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return false;
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// Handle *simple* calls for now.
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const Type *RetTy = I->getType();
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EVT RetVT;
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if (RetTy->isVoidTy())
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RetVT = MVT::isVoid;
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else if (!isTypeLegal(RetTy, RetVT))
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return false;
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// For now we're using BLX etc on the assumption that we have v5t ops.
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// TODO: Maybe?
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if (!Subtarget->hasV5TOps()) return false;
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// Set up the argument vectors.
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SmallVector<Value*, 8> Args;
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SmallVector<unsigned, 8> ArgRegs;
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SmallVector<EVT, 8> ArgVTs;
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SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
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Args.reserve(CS.arg_size());
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ArgRegs.reserve(CS.arg_size());
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ArgVTs.reserve(CS.arg_size());
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ArgFlags.reserve(CS.arg_size());
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for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
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i != e; ++i) {
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unsigned Arg = getRegForValue(*i);
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if (Arg == 0)
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return false;
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ISD::ArgFlagsTy Flags;
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unsigned AttrInd = i - CS.arg_begin() + 1;
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if (CS.paramHasAttr(AttrInd, Attribute::SExt))
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Flags.setSExt();
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if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
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Flags.setZExt();
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// FIXME: Only handle *easy* calls for now.
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if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
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CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
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CS.paramHasAttr(AttrInd, Attribute::Nest) ||
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CS.paramHasAttr(AttrInd, Attribute::ByVal))
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return false;
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const Type *ArgTy = (*i)->getType();
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EVT ArgVT;
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if (!isTypeLegal(ArgTy, ArgVT))
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return false;
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unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Args.push_back(*i);
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ArgRegs.push_back(Arg);
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ArgVTs.push_back(ArgVT);
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ArgFlags.push_back(Flags);
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}
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// Handle the arguments now that we've gotten them.
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SmallVector<unsigned, 4> RegArgs;
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unsigned NumBytes;
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if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
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return false;
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// Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
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// TODO: Turn this into the table of arm call ops.
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MachineInstrBuilder MIB;
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unsigned CallOpc;
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if(isThumb)
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CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
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else
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CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
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.addGlobalAddress(GV, 0, 0);
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// Add implicit physical register uses to the call.
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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MIB.addReg(RegArgs[i]);
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// Finish off the call including any return values.
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SmallVector<unsigned, 4> UsedRegs;
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if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
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// Set all unused physreg defs as dead.
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static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
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return true;
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}
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// TODO: SoftFP support.
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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// No Thumb-1 for now.
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@ -1261,6 +1401,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return SelectBinaryOp(I, ISD::FMUL);
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case Instruction::SDiv:
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return SelectSDiv(I);
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case Instruction::Call:
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return SelectCall(I);
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default: break;
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}
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return false;
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