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Merge my changes with brians

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-04-07 04:05:49 +00:00
parent 0f51cc1759
commit f97b31e9cf
2 changed files with 10 additions and 12 deletions
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11
lib/Target/Sparc/SparcRegisterInfo.td
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@ -24,16 +24,12 @@ class Rf<bits<5> num> : Register {
class Rd<bits<5> num> : Register {
field bits<5> Num = num;
}
// Rs - Special "ancillary state registers"
// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
// WIM, TBR, etc registers
class Rs<bits<5> num> : Register {
field bits<5> Num = num;
}
// Special register used for multiplies and divides
let Namespace = "V8" in {
def Y : Rs<0>;
}
let Namespace = "V8" in {
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
@ -62,6 +58,9 @@ let Namespace = "V8" in {
def D4 : Rd< 8>; def D5 : Rd<10>; def D6 : Rd<12>; def D7 : Rd<14>;
def D8 : Rd<16>; def D9 : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
// The Y register.
def Y : Rs<0>;
}

11
lib/Target/SparcV8/SparcV8RegisterInfo.td
View File

@ -24,16 +24,12 @@ class Rf<bits<5> num> : Register {
class Rd<bits<5> num> : Register {
field bits<5> Num = num;
}
// Rs - Special "ancillary state registers"
// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
// WIM, TBR, etc registers
class Rs<bits<5> num> : Register {
field bits<5> Num = num;
}
// Special register used for multiplies and divides
let Namespace = "V8" in {
def Y : Rs<0>;
}
let Namespace = "V8" in {
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
@ -62,6 +58,9 @@ let Namespace = "V8" in {
def D4 : Rd< 8>; def D5 : Rd<10>; def D6 : Rd<12>; def D7 : Rd<14>;
def D8 : Rd<16>; def D9 : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>;
def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>;
// The Y register.
def Y : Rs<0>;
}